Hiroaki Yamaoka

According to our database, Hiroaki Yamaoka authored at least 5 papers between 2001 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2005

A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells.

Ulkuhan Ekinciel, Hiroaki Yamaoka, Hiroaki Yoshida, Makoto Ikeda, Kunihiro Asada

IEICE Trans. Inf. Syst., 2005

2003

A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design.

Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada

Proceedings of the ESSCIRC 2003, 2003

2002

Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA.

Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Logic synthesis for PLA with 2-input logic elements.

Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme.

Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada

Proceedings of ASP-DAC 2001, 2001