Hiroaki Ueno

According to our database, Hiroaki Ueno authored at least 5 papers between 2002 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

30.5 A GaN 3×3 matrix converter chipset with Drive-by-Microwave technologies.

Shuichi Nagai, Yasuhiro Yamada, Noboru Negoro, Hiroyuki Handa, Yuji Kudoh, Hiroaki Ueno, Masahiro Ishida, Nobuyuki Otuska, Daisuke Ueda

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2005

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential.

Dondee Navarro, Takeshi Mizoguchi, Masami Suetake, Kazuya Hisamitsu, Hiroaki Ueno, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama

IEICE Trans. Electron., 2005

1/<i>f</i>-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation.

Shizunori Matsumoto, Hiroaki Ueno, Satoshi Hosokawa, Toshihiko Kitamura, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama

IEICE Trans. Electron., 2005

2003

Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design.

Kazuya Hisamitsu, Hiroaki Ueno, Masayasu Tanaka, Daisuke Kitamaru, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Circuit Simulation Models for Coming MOSFET Generations.

Mitiko Miura-Mattausch, Hiroaki Ueno, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002