Hiroaki Shikano

According to our database, Hiroaki Shikano authored at least 10 papers between 2003 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

QoS Analysis on Cable Video Delivery Networks.

Hiroaki Shikano, Takeshi Shibata, Qifeng Shen, Miyuki Hanaoka, Mariko Miyaki, Masahide Ban, Prasad Rallapalli, Yukinori Sakashita

Proceedings of the 14th International Joint Conference on e-Business and Telecommunications (ICETE 2017), 2017

2013

Study on supporting technology for operational procedure design of IT systems in cloud-era datacenters.

Hiroaki Shikano, Machiko Asaie, Junji Yamamoto, Tatsuya Saito, Shunsuke Ota, Keitaro Uehara

Proceedings of the 28th Annual ACM Symposium on Applied Computing, 2013

2011

A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture.

Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Trans. High Perform. Embed. Archit. Compil., 2011

2008

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding.

Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

IEEE J. Solid State Circuits, 2008

Power-Aware Compiler Controllable Chip Multiprocessor.

Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

IEICE Trans. Electron., 2008

Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array.

Tadayoshi Enomoto, Suguru Nagayama, Hiroaki Shikano, Yousuke Hagiwara

IEICE Trans. Electron., 2008

Software-cooperative power-efficient heterogeneous multi-core for media processing.

Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2005

Compiler Control Power Saving Scheme for Multi Core Processors.

Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Proceedings of the Languages and Compilers for Parallel Computing, 2005

Performance Evaluation of Compiler Controlled Power Saving Scheme.

Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

2003

A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications.

Tadayoshi Enomoto, Yoshinori Oka, Hiroaki Shikano

IEEE J. Solid State Circuits, 2003