Hiroaki Nambu

According to our database, Hiroaki Nambu authored at least 8 papers between 1992 and 2000.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2000

Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions.

Takeshi Suzuki, Keiichi Higeta, Yasuhiro Fujimura, Kazumasa Ando, Hiroaki Nambu, Ryo Yamagata, Atsuo Hotta, Kunihiko Yamaguchi

IEEE J. Solid State Circuits, 2000

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz.

Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta

IEEE J. Solid State Circuits, 2000

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM.

Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma

IEEE J. Solid State Circuits, 2000

1998

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM.

Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Yasuhiro Fujimura, Kazumasa Ando, Takeshi Kusunoki, Kunihiko Yamaguchi, Noriyuki Homma

IEEE J. Solid State Circuits, 1998

1996

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry.

Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta

IEEE J. Solid State Circuits, 1996

1994

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates.

Nobuo Tamba, Akio Anzai, Kazuhiro Akimoto, Masayuki Ohayashi, Toshiro Hiramoto, Tadanori Kokubu, Sohei Ohmori, Tetsuya Muraya, Atsuyuki Kishimoto, Sousuke Tsuji, Hideki Hayashi, Nadateru Handa, Toshio Igarashi, Hiroaki Nambu, Makoto Yoshida, Tsuyoshi Fujiwara, Kunihiko Watanabe, Akihisa Uchida, Masanori Odaka, Kunihiko Yamaguchi, Takahide Ikeda

IEEE J. Solid State Circuits, November, 1994

1992

High-speed sensing techniques for ultrahigh-speed SRAMs.

Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Kunihiko Yamaguchi, Toshiro Hiramoto, Nobuo Tamba, Masanori Odaka, Kunihiko Watanabe, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai

IEEE J. Solid State Circuits, April, 1992

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM.

Kunihiko Yamaguchi, Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Toshiro Hiramoto, Nobuo Tamba, Kunihiko Watanabe, Masanori Odaka, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai

IEEE J. Solid State Circuits, February, 1992