Hiroaki Matsushita

According to our database, Hiroaki Matsushita authored at least 6 papers between 2008 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

An on-die digital aging monitor against HCI and xBTI in 16 nm Fin-FET bulk CMOS technology.

Mitsuhiko Igarashi, Kan Takeuchi, Takeshi Okagaki, Koji Shibutani, Hiroaki Matsushita, Koji Nii

Proceedings of the ESSCIRC Conference 2015, 2015

2013

Spatial Distribution Measurement of Dynamic Voltage Drop Caused by Pulse and Periodic Injection of Spot Noise.

Kan Takeuchi, Masaki Shimada, Takao Sato, Yusaku Katsuki, Hiroumi Yoshikawa, Hiroaki Matsushita

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

28-nm HKMG GHz digital sensor for detecting dynamic voltage drops in testing for peak power optimization.

Mitsuhiko Igarashi, Kan Takeuchi, Yoshio Takazawa, Yasuto Igarashi, Hiroaki Matsushita

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2008

Clock-Skew Test Module for Exploring Reliable Clock-Distribution Under Process and Global Voltage-Temperature Variations.

Kan Takeuchi, Atsushi Yoshikawa, Michio Komoda, Ken Kotani, Hiroaki Matsushita, Yusaku Katsuki, YuyoYamamoto, Takao Sato

IEEE Trans. Very Large Scale Integr. Syst., 2008

Observations of Supply-Voltage-Noise Dispersion in Sub-nsec.

Kan Takeuchi, Genichi Tanaka, Hiroaki Matsushita, Kenichi Yoshizumi, Yusaku Katsuki, Takao Sato

Proceedings of the 2008 IEEE International Test Conference, 2008

A voltage drop aware crosstalk measurement with multi-aggressors in 65nm process.

Genichi Tanaka, Kan Takeuchi, Minoru Ito, Hiroaki Matsushita

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008