Hiroaki Kunieda

According to our database¹, Hiroaki Kunieda authored at least 61 papers between 1995 and 2017.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

Dataset

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Links

On csauthors.net:

Bibliography

2017

Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2017

HOG-Based Object Detection Processor Design Using ASIP Methodology.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Narrow Fingerprint Template Synthesis by Clustering Minutiae Descriptors.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2017

Hybrid Minutiae Descriptor for Narrow Fingerprint Verification.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2017

2016

Efficient Synchronization for Distributed Embedded Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Fast Trace Aware Statistical Based Prediction Model with Burst Traffic Modeling for Contention Stall in A Priority Based MPSoC Bus.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2016

An efficient embedded processor for object detection using ASIP methodology.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015

Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension.

[BibT_eX]

[DOI]

J. Inf. Process., 2015

Efficient Design Exploration Framework of SW/HW Systems Based on Tightly-coupled Thread Model.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2015

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Online Detection of Spoof Fingers for Smartphone-Based Applications.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014

A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach.

[BibT_eX]

[DOI]

J. Inf. Process., 2014

Retargeting Derivative-ASIP with Assembly Converter Tool.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Distributed synchronization for message-passing based embedded multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Dalvik bytecode acceleration using Fetch/Decode Hardware Extension with hybrid Execution.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Custom instruction search for application specific instruction-set processor using guided simulated annealing.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing.

[BibT_eX]

[DOI]

J. Inf. Process., 2013

A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2012

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2012

A Low-Cost and Energy-Efficient Multiprocessor System-on-Chip for UWB MAC Layer.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

Narrow Fingerprint Sensor Verification with Template Updating Technique.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Application-specific Instruction-Set Processor design methodology for wireless image transmission systems.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

Robust Multiple Minutiae Partitions for Fingerprint Authentication.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Symposium on Biometrics and Security Technologies, 2012

A Reconfigurable High Performance ASIP Engine for Image Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2012

A reconfigurable ASIP-based approach for high performance image signal processing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Unique Fingerprint-Image-Generation Algorithm for Line Sensors.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Practical Orientation Field Estimation for Embedded Fingerprint Recognition Systems.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2011

2010

A Unified Performance Estimation Method for Hardware and Software Components in Multiprocessor System-On-Chips.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2010

Orientation Field Estimation for Embedded Fingerprint Authentication System.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2010

Ultra fast fingerprint indexing for embedded system.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference of Soft Computing and Pattern Recognition, 2010

A novel similarity measurement for minutiae-based fingerprint verification.

[BibT_eX]

[DOI]

Proceedings of the Fourth IEEE International Conference on Biometrics: Theory Applications and Systems, 2010

2009

Entropy Decoding Processor for Modern Multimedia Applications.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Trace-driven workload simulation method for Multiprocessor System-On-Chips.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC.

[BibT_eX]

[DOI]

Mohammad Zalfany Urfianto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development.

[BibT_eX]

[DOI]

Mohammad Zalfany Urfianto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

MAPS: an integrated framework for MPSoC application parallelization.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

H.264/AVC decoder SoC towards the low cost mobile video player.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International SOC Conference, 2007

2005

A Fingerprint Matching Using Minutia Ridge Shape for Low Cost Match-on-Card Systems.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

New Macroblock Engine Architecture for Video Processing.

[BibT_eX]

[DOI]

Proceedings of the IAPR Conference on Machine Vision Applications (IAPR MVA 2005), 2005

A Hybrid Method for Fingerprint Image Quality Calculation.

[BibT_eX]

[DOI]

Proceedings of the Fourth IEEE Workshop on Automatic Identification Advanced Technologies (AutoID 2005), 2005

2003

A false-lock-free clock/data recovery PLL for NRZ data using adaptive phase frequency detector.

[BibT_eX]

[DOI]

Gijun Idei

Hiroaki Kunieda

IEEE Trans. Circuits Syst. II Express Briefs, 2003

2002

New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Realization of fingerprint identification module on DSP board.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

High density bit-serial FPGA with LUT embedding shift register function.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

A new methodology for low delay real-time videophone software architecture design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Efficient method for face region quality enhancement in low bit rate video coding.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

H.263+ Video Encoder/Decoder LSI Featuring System-MSPA Architecture and Improved Rate Control Method.

[BibT_eX]

Proceedings of the World Multiconference on Systemics, Cybernetics and Informatics, 2001

2000

Cost-effective shadowing method using the ED-buffer on an adaptive light cube.

[BibT_eX]

[DOI]

Tsuyoshi Isshiki

Makoto Ishikawa

Hiroaki Kunieda

Vis. Comput., 2000

1999

Efficient anti-aliasing algorithm for computer generated images.

[BibT_eX]

[DOI]

Tsuyoshi Isshiki

Hiroaki Kunieda

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Motion Estimator LSI for MPEG2 High Level Standard.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract).

[BibT_eX]

[DOI]

Tsuyoshi Isshiki

Takenobu Shimizugashira

Akihisa Ohta

Imanuddin Amril

Hiroaki Kunieda

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

New FPGA Architecture for Bit-Serial Pipeline Datapath.

[BibT_eX]

[DOI]

Akihisa Ohta

Tsuyoshi Isshiki

Hiroaki Kunieda

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

Towards one chip HDTV MPEG2 encoder LSI.

[BibT_eX]

[DOI]

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

FPGA for High-Performance Bit-Serial Pipeline Datapath.

[BibT_eX]

[DOI]

Tsuyoshi Isshiki

Takenobu Shimizugashira

Akihisa Ohta

Imanuddin Amril

Hiroaki Kunieda

Proceedings of the ASP-DAC '98, 1998

1997

High speed bit-serial parallel processing on array architecture.

[BibT_eX]

[DOI]

Kazuhito Ito

Takenobu Shimizugashira

Hiroaki Kunieda

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

Bit-serial pipeline synthesis and layout for large-scale configurable systems.

[BibT_eX]

[DOI]

Tsuyoshi Isshiki

Wayne Wei-Ming Dai

Hiroaki Kunieda

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1995

Automatic design for bit-serial MSPA architecture.

[BibT_eX]

[DOI]

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

Hiroaki Kunieda

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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