Hiroaki Kotani

According to our database, Hiroaki Kotani authored at least 5 papers between 1990 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

An Energy-Efficient ΔΣ Modulator Using Dynamic-Common-Source Integrators.

Ryo Matsushiba, Hiroaki Kotani, Takao Waho

IEICE Trans. Electron., 2014

2012

Energy Efficiency of Multi-bit delta-sigma Modulators Using Inverter-based Integrators.

Hiroaki Kotani, Ryoto Yaguchi, Takao Waho

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

2001

A 126.6-mm² AND-type 512-Mb flash memory with 1.8-V power supply.

Tatsuya Ishii, Kazuyoshi Oshima, Hiroshi Sato, Satoshi Noda, Jiro Kishimoto, Hiroaki Kotani, Atsushi Nozoe, Kazunori Furusawa, Takayuki Yoshitake, Masataka Kato, Masahito Takahashi, Akihiko Sato, Shoji Kubono, Kiichi Manita, Kenji Koda, Takeshi Nakayama, Akira Hosogane

IEEE J. Solid State Circuits, 2001

1999

A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications.

Atsushi Nozoe, Hiroaki Kotani, Tetsuya Tsujikawa, Keiichi Yoshida, Kazunori Furusawa, Masataka Kato, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Kurata, Naoki Miyamoto, Shoji Kubono, Michitaro Kanamitsu, Kenji Koda, Takeshi Nakayama, Yasuhiro Kouro, Akira Hosogane, Natsuo Ajika, Kiyoteru Kobayashi

IEEE J. Solid State Circuits, 1999

1990

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier.

Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto

IEEE J. Solid State Circuits, October, 1990