Hiroaki Inoue

According to our database1, Hiroaki Inoue authored at least 58 papers between 1988 and 2022.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2005, "For contributions to semiconductor optical switches and modulators.".

Timeline

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Links

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Bibliography

2022
Automated formal analysis of temporal properties of Ladder programs.
Int. J. Softw. Tools Technol. Transf., 2022

Estimating Distributions of Parameters in Nonlinear State Space Models with Replica Exchange Particle Marginal Metropolis-Hastings Method.
Entropy, 2022

2021
Automated Verification of Temporal Properties of Ladder Programs.
Proceedings of the Formal Methods for Industrial Critical Systems, 2021

2020
Basic Study to Reduce the Artifact from Brain Activity Data with Auto-regressive Model.
Proceedings of the HCI International 2020 - Late Breaking Papers: Cognition, Learning and Games, 2020

Basic Study on Measuring Brain Activity for Evaluation Method of Visually Impaired Person's Orientation and Mobility Skills.
Proceedings of the HCI International 2020 - Late Breaking Posters, 2020

Fundamental Study for Analysis of Walking Considering Base of Support for Prevention of Stumble Accident.
Proceedings of the HCI International 2020 - Late Breaking Posters, 2020

2019
A type system for first-class layers with inheritance, subtyping, and swapping.
Sci. Comput. Program., 2019

Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA.
IPSJ Trans. Syst. LSI Des. Methodol., 2019

Automated Deductive Verification for Ladder Programming.
Proceedings of the Proceedings Fifth Workshop on Formal Integrated Development Environment, 2019

2018
A Language-Based Approach to Robust Context-Aware Software.
PhD thesis, 2018

ContextWorkflow: A Monadic DSL for Compensable and Interruptible Executions (Artifact).
Dagstuhl Artifacts Ser., 2018

Parallel Rate Distortion Optimized Quantization for 4K Real-time GPU-based HEVC Encoder.
Proceedings of the IEEE Visual Communications and Image Processing, 2018

ContextWorkflow: A Monadic DSL for Compensable and Interruptible Executions.
Proceedings of the 32nd European Conference on Object-Oriented Programming, 2018

2017
A DSL for compensable and interruptible executions.
Proceedings of the 4th ACM SIGPLAN International Workshop on Reactive and Event-Based Languages and Systems, 2017

2016
A library-based approach to context-dependent computation with reactive values: suppressing reactions of context-dependent functions using dynamic binding.
Proceedings of the Companion Proceedings of the 15th International Conference on Modularity, Málaga, Spain, March 14, 2016

2015
Enhancing Memcached by Caching Its Data and Functionalities at Network Interface.
J. Inf. Process., 2015

Network-Level FPGA Acceleration of Low Latency Market Data Feed Arbitration.
IEICE Trans. Inf. Syst., 2015

FPGA-accelerated complex event processing.
Proceedings of the Symposium on VLSI Circuits, 2015

Consideration of Measuring Human Physical and Psychological Load Based on Brain Activity.
Proceedings of the Universal Access in Human-Computer Interaction. Access to Today's Technologies, 2015

A Sound Type System for Layer Subtyping and Dynamically Activated First-Class Layers.
Proceedings of the Programming Languages and Systems - 13th Asian Symposium, 2015

2014
Basic Study for New Assistive Technology Based on Brain Activity During Car Driving.
J. Robotics Mechatronics, 2014

Consideration for Interpretation of Brain Activity Pattern during Car Driving Based on Human Movements.
Proceedings of the Design, User Experience, and Usability. User Experience Design Practice, 2014

Attempts to Quantitative Analyze for the Change of Human Brain Activity with Physical and Psychological Load.
Proceedings of the Design, User Experience, and Usability. Theories, Methods, and Tools for Designing the User Experience, 2014

Achieving higher performance of memcached by caching at network interface.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Caching memcached at reconfigurable network interface.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Towards Type-Safe JCop: A type system for layer inheritance and first-class layers.
Proceedings of 6th International Workshop on Context-Oriented Programming, 2014

Mapping complex algorithm into FPGA with High Level Synthesis reconfigurable chips with High Level Synthesis compared with CPU, GPGPU.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Low latency FPGA acceleration of market data feed arbitration.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
C-Based Complex Event Processing on Reconfigurable Hardware.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Exploiting hardware reconfigurability on window join.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013

Human Support System for Elderly People in Daily Life.
Proceedings of the Human Interface and the Management of Information. Information and Interaction for Health, Safety, Mobility and Complex Environments, 2013

Fundamental Study for New Evaluation Method Based on Physical and Psychological Load in Human Movement.
Proceedings of the HCI International 2013 - Posters' Extended Abstracts, 2013

Application-specific customisation of market data feed arbitration.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Development of Hybrid Hydraulic Excavators.
Int. J. Autom. Technol., 2012

A scalable complex event processing framework for combination of SQL-based continuous queries and C/C++ functions.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Dynamic query switching for complex event processing on FPGAs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Fundamental study to new assist system for wheel chair based on brain activity during car driving.
Proceedings of the 5th International Conference on BioMedical Engineering and Informatics, 2012

2011
Test compression for dynamically reconfigurable processors.
ACM Trans. Reconfigurable Technol. Syst., 2011

Basic study for a new assistive system based on brain activity associated with spatial perception task during car driving.
Proceedings of the 2011 IEEE International Conference on Robotics and Biomimetics, 2011

Basic Study of Analysis of Human Brain Activities during Car Driving.
Proceedings of the Human Interface and the Management of Information. Interacting with Information, 2011

Greening of Many-Core Processors in Network-Optimized Computing.
Proceedings of the Global Communications Conference, 2011

20Gbps C-Based Complex Event Processing.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Fundamental Study for Human Brain Activity Based on the Spatial Cognitive Task.
Proceedings of the Brain Informatics - International Conference, 2011

2010
A robust seamless communication architecture for next-generation mobile terminals on multi-CPU SoCs.
ACM Trans. Embed. Comput. Syst., 2010

A Multi-Core Processor Platform for Open Embedded Systems
CoRR, 2010

Onix: A Distributed Control Platform for Large-scale Production Networks.
Proceedings of the 9th USENIX Symposium on Operating Systems Design and Implementation, 2010

Test Compression for Dynamically Reconfigurable Processors.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Dynamic security domain scaling on embedded symmetric multiprocessors.
ACM Trans. Design Autom. Electr. Syst., 2009

2008
Processor virtualization for secure mobile terminals.
ACM Trans. Design Autom. Electr. Syst., 2008

FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals.
ACM Trans. Embed. Comput. Syst., 2008

Multitasking Parallel Method for High-End Embedded Appliances.
IEEE Micro, 2008

VAST: Virtualization-Assisted Concurrent Autonomous Self-Test.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Towards scalable and secure execution platform for embedded systems.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals.
Proceedings of the 43rd Design Automation Conference, 2006

2005
FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

1988
An 8 mm length nonblocking 4×4 optical switch array.
IEEE J. Sel. Areas Commun., 1988


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