Hiroaki Hoshino

According to our database1, Hiroaki Hoshino authored at least 11 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018

2014
20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication".
IEEE J. Solid State Circuits, 2013

2012
A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication.
IEEE J. Solid State Circuits, 2012

A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2010
A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications.
IEEE J. Solid State Circuits, 2010

2009
A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS.
IEICE Trans. Electron., 2009

2008
A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer.
IEEE J. Solid State Circuits, 2008

2007
Dynamic Hybrid Type Mining in an Intelligent e-Government Model.
Proceedings of the 2007 IEEE/WIC/ACM International Conference on Web Intelligence and International Conference on Intelligent Agent Technology, 2007

A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2004
Modelling and optimization of on-chip spiral inductor in S-parameter domain.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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