Hiran Tennakoon

According to our database, Hiran Tennakoon authored at least 6 papers between 2002 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Library-Based Cell-Size Selection Using Extended Logical Effort.

Mohammad Rahman, Hiran Tennakoon, Carl Sechen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2011

Power reduction via near-optimal library-based cell-size selection.

Mohammad Rahman, Hiran Tennakoon, Carl Sechen

Proceedings of the Design, Automation and Test in Europe, 2011

Power reduction via separate synthesis and physical libraries.

Mohammad Rahman, Ryan Afonso, Hiran Tennakoon, Carl Sechen

Proceedings of the 48th Design Automation Conference, 2011

2008

Nonconvex Gate Delay Modeling and Delay Optimization.

Hiran Tennakoon, Carl Sechen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2005

Efficient and accurate gate sizing with piecewise convex delay models.

Hiran Tennakoon, Carl Sechen

Proceedings of the 42nd Design Automation Conference, 2005

2002

Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step.

Hiran Tennakoon, Carl Sechen

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002