Hing Wong

According to our database, Hing Wong authored at least 4 papers between 1996 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

A 220-mm², four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.

Toshiaki Kirihata, Martin Gall, Kohji Hosokawa, Jean-Marc Dortu, Hing Wong, Peter Pfefferl, Brian L. Ji, Oliver Weinfurtner, John K. DeBrosse, Hartmud Terletzki, Manfred Selz, Wayne Ellis, Matthew R. Wordeman, Oliver Kiehl

IEEE J. Solid State Circuits, 1998

1997

Flexible test mode approach for 256-Mb DRAM.

Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik

IEEE J. Solid State Circuits, 1997

Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip.

W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

Fault-tolerant designs for 256 Mb DRAM.

Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao

IEEE J. Solid State Circuits, 1996