Himanshu Thapliyal

IEEE Consumer Electron. Mag., 2018

Solar Cell Based Physically Unclonable Function for Cybersecurity in IoT Devices.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Amazon Echo Enabled IoT Home Security System for Smart Home Environment.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Towards Photoplethysmogram Based Non-Invasive Blood Pressure Classification.

[BibT_eX]

[DOI]

Rajdeep Kumar Nath

Allison Caban-Holt

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Hardware Trojan Detection in Implantable Medical Devices Using Adiabatic Computing.

[BibT_eX]

[DOI]

Zach Kahleifeh

Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Energy-recovery based hardware security primitives for low-power embedded devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Panel theme: Energy and cybersecurity constraints on consumer electronics.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2018

IoT based indoor location detection system for smart home environment.

[BibT_eX]

[DOI]

Rajdeep Kumar Nath

Rajnish Bajpai

Proceedings of the IEEE International Conference on Consumer Electronics, 2018

T-count Optimized Quantum Circuits for Bilinear Interpolation.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

2017

Automatic synthesis of quaternary quantum circuits.

[BibT_eX]

[DOI]

Mozammel H. A. Khan

J. Supercomput., 2017

Efficient Circuit Design of Reversible Square.

[BibT_eX]

[DOI]

H. V. Jayashree

Vinod Kumar Agrawal

Trans. Comput. Sci., 2017

Energy-efficient magnetic 4-2 compressor.

[BibT_eX]

[DOI]

Microelectron. J., 2017

Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware.

[BibT_eX]

[DOI]

Integr., 2017

T-count Optimized Design of Quantum Integer Multiplication.

[BibT_eX]

[DOI]

CoRR, 2017

Stress Detection and Management: A Survey of Wearable Smart Health Devices.

[BibT_eX]

[DOI]

Vladislav Khalus

IEEE Consumer Electron. Mag., 2017

Heuristic Based Majority/Minority Logic Synthesis for Emerging Technologies.

[BibT_eX]

[DOI]

Vipul Kumar Mishra

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices.

[BibT_eX]

[DOI]

T. S. S. Varun

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Design of Quantum Circuits for Galois Field Squaring and Exponentiation.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Quantum Circuit Designs of Integer Division Optimizing T-Count and T-Depth.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

Security Evaluation of MTJ/CMOS Circuits Against Power Analysis Attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

Energy-efficient magnetic circuits based on nanoelectronic devices.

[BibT_eX]

[DOI]

Fazel Sharifi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design of majority logic based approximate arithmetic circuits.

[BibT_eX]

[DOI]

Fabrizio Lombardi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Low-Power and Secure Lightweight Cryptography Via TFET-Based Energy Recovery Circuits.

[BibT_eX]

[DOI]

T. S. S. Varun

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

UTB-SOI based adiabatic computing for low-power and secure IoT devices.

[BibT_eX]

[DOI]

T. S. S. Varun

Proceedings of the 12th Annual Conference on Cyber and Information Security Research, 2017

2016

Erratum to: Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines.

[BibT_eX]

[DOI]

Ke Chen

J. Supercomput., 2016

Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines.

[BibT_eX]

[DOI]

Ke Chen

J. Supercomput., 2016

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier.

[BibT_eX]

[DOI]

J. Supercomput., 2016

Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates.

[BibT_eX]

[DOI]

Trans. Comput. Sci., 2016

Design Methodologies for Reversible Logic Based Barrel Shifters.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

A Survey of Affective Computing for Stress Detection: Evaluating technologies in stress detection for better health.

[BibT_eX]

[DOI]

Shalom Greene

Allison Caban-Holt

IEEE Consumer Electron. Mag., 2016

Design of quaternary 4-2 and 5-2 compressors for nanotechnology.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2016

Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic Logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Exploring Human Body Communications for IoT Enabled Ambulatory Health Monitoring Systems.

[BibT_eX]

[DOI]

Prabha Sundaravadivel

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

IoT-Based Fall Detection for Smart Home Environments.

[BibT_eX]

[DOI]

Shalom Greene

David Carpenter

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

FinSAL: A novel FinFET based Secure Adiabatic Logic for energy-efficient and DPA resistant IoT devices.

[BibT_eX]

[DOI]

Azhar Mohammad

Proceedings of the IEEE International Conference on Rebooting Computing, 2016

QUALPUF: A Novel Quasi-Adiabatic Logic based Physical Unclonable Function.

[BibT_eX]

[DOI]

Proceedings of the 11th Annual Cyber and Information Security Research Conference, 2016

2015

Reversible logic based multiplication computing unit using binary tree data structure.

[BibT_eX]

[DOI]

J. Supercomput., 2015

Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression.

[BibT_eX]

[DOI]

Mozammel H. A. Khan

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Design of Testable Adder Circuits for Spintronics Based Nanomagnetic Computing.

[BibT_eX]

[DOI]

Ronald F. DeMara

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014

Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits.

[BibT_eX]

[DOI]

Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain.

[BibT_eX]

[DOI]

Trans. Comput. Sci., 2014

Efficient reversible NOR gates and their mapping in optical computing domain.

[BibT_eX]

[DOI]

Microelectron. J., 2014

Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Design of Dedicated Reversible Quantum Circuitry for Square Computation.

[BibT_eX]

[DOI]

H. V. Jayashree

Vinod Kumar Agrawal

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013

Design of Testable Reversible Sequential Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder.

[BibT_eX]

[DOI]

Trans. Comput. Sci., 2013

Design of efficient reversible logic-based binary and BCD adder circuits.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

A new CRL gate as super class of Fredkin gate to design reversible quantum circuits.

[BibT_eX]

[DOI]

Apeksha Bhatt

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012

Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Mach-Zehnder interferometer based design of all optical reversible binary adder.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies.

[BibT_eX]

[DOI]

PhD thesis, 2011

Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits

[BibT_eX]

[DOI]

CoRR, 2011

A new reversible design of BCD adder.

[BibT_eX]

[DOI]

N. Ranganathan

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2010

Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009

Efficient Reversible Logic Design of BCD Subtractors.

[BibT_eX]

[DOI]

Trans. Comput. Sci., 2009

Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007

Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs.

[BibT_eX]

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

Designing Efficient Online Testable Reversible Adders With New Reversible Gate.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design of Reversible Sequential Elements With Feasibility of Transistor Implementation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Partial Reversible Gates(PRG) for Reversible BCD Arithmetic.

[BibT_eX]

Proceedings of the 2007 International Conference on Computer Design, 2007

2006

Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation

[BibT_eX]

[DOI]

CoRR, 2006

Reversible Logic to Cryptographic Hardware: A New Paradigm

[BibT_eX]

[DOI]

Mark Zwolinski

CoRR, 2006

Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format

[BibT_eX]

[DOI]

CoRR, 2006

Reversible Programmable Logic Array (RPLA) using Fredkin & Feynman Gates for Industrial Electronics and Applications

[BibT_eX]

[DOI]

CoRR, 2006

VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics

[BibT_eX]

[DOI]

CoRR, 2006

Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU

[BibT_eX]

[DOI]

CoRR, 2006

An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates

[BibT_eX]

[DOI]

CoRR, 2006

A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits

[BibT_eX]

[DOI]

CoRR, 2006

Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations.

[BibT_eX]

Pallavi Devi Gopineedi

Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

Design of Novel Reversible Carry Look-Ahead BCD Subtractor.

[BibT_eX]

[DOI]

Sumedha K. Gupta

Proceedings of the 9th International Conference in Information Technology, 2006

A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs.

[BibT_eX]

Vishal Verma

Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations.

[BibT_eX]

Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications.

[BibT_eX]

Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation.

[BibT_eX]

Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Novel Reversible Multiplier Architecture Using Reversible TSG Gate.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

The New BCD Subtractor and Its Reversible Logic Implementation.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005

Implementation of A Fast Square In RSA Encryption/Decryption Architecture.

[BibT_eX]

Proceedings of The 2005 International Conference on Security and Management, 2005

Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier.

[BibT_eX]

Proceedings of The 2005 International Conference on Security and Management, 2005

Reversible Logic Synthesis of Half, Full and Parallel Subtractors.

[BibT_eX]

Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs.

[BibT_eX]

Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor.

[BibT_eX]

Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison.

[BibT_eX]

Proceedings of The 2005 International Conference on Scientific Computing, 2005

Verilog Coding Style for Efficient Synthesis In FPGA.

[BibT_eX]

Proceedings of the 2005 International Conference on Computer Design, 2005

Design for A Fast And Low Power 2's Complement Multiplier.

[BibT_eX]

Proceedings of the 2005 International Conference on Computer Design, 2005

Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture.

[BibT_eX]

Proceedings of the 2005 International Conference on Algorithmic Mathematics and Computer Science, 2005

A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004

A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics.

[BibT_eX]

Proceedings of the International Conference on Embedded Systems and Applications, 2004

A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics.

[BibT_eX]

Proceedings of the International Conference on Embedded Systems and Applications, 2004

High Speed Efficient N Bit by N Bit Division Algorithm and Architecture Based on Ancient Indian Vedic Mathematics.

[BibT_eX]

Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003

A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics.

[BibT_eX]

Vishal Verma