Himadri Singh Raghav

According to our database1, Himadri Singh Raghav authored at least 10 papers between 2013 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2020
Investigating the influence of adiabatic load on the 4-phase adiabatic system design.
Integr., 2020

2019
A balanced power analysis attack resilient adiabatic logic using single charge sharing transistor.
Integr., 2019

2018
Investigating the effectiveness of Without Charge-Sharing Quasi-Adiabatic Logic for energy efficient and secure cryptographic implementations.
Microelectron. J., 2018

Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

2017
Robustness of power analysis attack resilient adiabatic logic: WCS-QuAL under PVT variations.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

A novel power analysis attack resilient adiabatic logic without charge sharing.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016
Energy efficiency of 2-step charging power-clock for adiabatic logic.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2013
Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Characterization of Logical Effort for Improved Delay.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013


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