Hikaru Takayashiki

According to our database, Hikaru Takayashiki authored at least 7 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A New Sparse GEneral Matrix-matrix Multiplication Method for Long Vector Architecture by Hierarchical Row Merging.

Hikaru Takayashiki, Hotaka Yagi, Hiroki Nishimoto, Naoki Yoshifuji

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

2022

A Metadata Prefetching Mechanism for Hybrid Memory Architectures.

Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

IEICE Trans. Electron., 2022

Page-Address Coalescing of Vector Gather Instructions for Efficient Address Translation.

Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

Proceedings of the 12th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, 2022

2021

Register Flush-free Runahead Execution for Modern Vector Processors.

Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

2019

A Skewed Multi-banked Cache for Many-core Vector Processors.

Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

Supercomput. Front. Innov., 2019

An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems.

Masayuki Sato, Takuya Toyoshima, Hikaru Takayashiki, Ryusuke Egawa, Hiroaki Kobayashi

Supercomput. Front. Innov., 2019

A Hardware Prefetching Mechanism for Vector Gather Instructions.

Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

Proceedings of the 9th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, 2019