Hideyuki Sugita

According to our database, Hideyuki Sugita authored at least 5 papers between 2004 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

A 16Gb/s 1^st-Tap FFE and 3-Tap DFE in 90nm CMOS.

Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications.

Tsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Hideyuki Sugita, Yoichi Yoshida, Masayuki Mizuno, Tadahiro Kuroda

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

An 18Gb/s duobinary receiver with a CDR-assisted DFE.

Kazuhisa Sunaga, Hideyuki Sugita, Koichi Yamaguchi, Kazumasa Suzuki

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology.

Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Tatsuya Ito, Kazuhisa Itoi, Masakazu Sato, Ryozo Yamauchi, Kazuya Masu

IEICE Trans. Electron., 2007

2004

High speed and low power on-chip micro network circuit with differential transmission line.

Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Kazuya Masu

Proceedings of the 2004 International Symposium on System-on-Chip, 2004