Hideto Hidaka
According to our database1,
Hideto Hidaka
authored at least 32 papers
between 1986 and 2020.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2017, "For leadership in high-density memory technologies for automotive applications".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age.
IEICE Trans. Electron., 2020
2019
A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications.
IEICE Trans. Electron., 2019
2018
Proceedings of the Embedded Flash Memory for Embedded Systems: Technology, 2018
Proceedings of the Embedded Flash Memory for Embedded Systems: Technology, 2018
2016
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C.
IEEE J. Solid State Circuits, 2016
7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
How future mobility meets IT: Cyber-physical system designs revisit semiconductor technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C.
IEEE J. Solid State Circuits, 2014
2013
40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2009
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2002
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability.
IEEE J. Solid State Circuits, 2002
A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
2001
IEEE J. Solid State Circuits, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
1999
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.
IEEE J. Solid State Circuits, 1999
1996
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories.
IEEE J. Solid State Circuits, 1996
1995
An automatic temperature compensation of internal sense ground for subquarter micron DRAM's.
IEEE J. Solid State Circuits, April, 1995
1994
IEEE J. Solid State Circuits, November, 1994
IEEE J. Solid State Circuits, November, 1994
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs.
IEEE J. Solid State Circuits, April, 1994
1993
IEEE Des. Test Comput., 1993
1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
1990
1989
IEEE J. Solid State Circuits, February, 1989
IEEE J. Solid State Circuits, February, 1989
1986
Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode.
Proceedings of the Proceedings International Test Conference 1986, 1986