Hideo Sawamoto

According to our database, Hideo Sawamoto authored at least 5 papers between 1995 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2004

Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI.

Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

1998

Instruction fetch and dispatch scheme with flag-in-cache/in-IBR.

Shoji Yoshida, Shigeya Tanaka, Kotaro Matsuo, Takashi Hotta, Hideo Sawamoto, Teruhisa Shimizu

Syst. Comput. Jpn., 1998

1996

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor.

Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto

IEEE J. Solid State Circuits, 1996

1995

A 13.3ns double-precision floating-point ALU and multiplier.

Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A superscalar RISC processor with pseudo vector processing feature.

Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995