Hideo Maejima

According to our database, Hideo Maejima authored at least 10 papers between 1983 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

IEICE Trans. Electron., 2011

2010

A 45nm 37.3GOPS/W heterogeneous multi-core SoC.

Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Domain Partitioning Technology for Embedded Multicore Processors.

Tohru Nojiri, Yuki Kondo, Naohiko Irie, Masayuki Ito, Hajime Sasaki, Hideo Maejima

IEEE Micro, 2009

TCBC: Trap Caching Bounds Checking for C.

Yoshitaka Arahori, Katsuhiko Gondow, Hideo Maejima

Proceedings of the Eighth IEEE International Conference on Dependable, 2009

1991

Fault-tolerant computer system with stepwise negotiating voting.

Nobuyasu Kanekawa, Hideo Maejima, Hatsuhiko Kato, Hirokazu Ihara

Syst. Comput. Jpn., 1991

1989

Circuit technologies for BiCMOS VLSI's as computer elements.

Hideo Maejima, Tadaaki Bandoh, Yoji Nishio, Tadashi Fukushima, Masanori Odaka, Atsuo Hotta

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

Dependable onboard computer systems with a new method-stepwise negotiating voting.

Nobuyasu Kanekawa, Hideo Maejima, Hatsuhiko Kato, Hirokazu Ihara

Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988

1.3- mu m CMOS/bipolar standard cell library for VLSI computers.

Takashi Hotta, Kouzaburou Kurita, Hideo Maejima, Masahiro Iwamura, Shigeya Tanaka, Tadaaki Bandoh, Tatsumi Yamauchi, Atsuo Hotta

IEEE J. Solid State Circuits, April, 1988

1986

A 16-Bit Microprocessor with Multi-Register Bank Architecture.

Hideo Maejima, Hiroyuki Kida, Tan Watanabe, Shiro Baba, Keiichi Kurakazu

Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

1983

The VLSI Control Structure of a CMOS Microcomputer.

Hideo Maejima, Koyo Katsura, Hideo Nakamura, Toshimasa Kihara

IEEE Micro, 1983