Hideo Ito

According to our database, Hideo Ito authored at least 76 papers between 1991 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

High-Efficiency Milling of Steam Turbine Blade.

Xin Yuan, Takanori Yazawa, Hideo Ito, Tatsuki Otsubo, Yukio Maeda, Reiko Yamada

Int. J. Autom. Technol., 2016

2014

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion.

Wenpo Zhang, Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2014

Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement.

Wenpo Zhang, Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2014

2013

Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF.

Wenpo Zhang, Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2013

Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA.

Kazuteru Namba, Nobuhide Takashina, Hideo Ito

IEICE Trans. Inf. Syst., 2013

Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop.

Kazuteru Namba, Takashi Katagiri, Hideo Ito

J. Electron. Test., 2013

2012

An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

IEEE Trans. Very Large Scale Integr. Syst., 2012

Improving small-delay fault coverage for on-chip delay measurement.

Wenpo Zhang, Kazuteru Namba, Hideo Ito

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Dual-edge-triggered FF with timing error detection capability.

Kazuteru Namba, Takashi Katagiri, Hideo Ito

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011

Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits.

Kazuteru Namba, Hideo Ito

IEEE Trans. Computers, 2011

Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture.

Kiyonori Matsumoto, Kazuteru Namba, Hideo Ito

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Construction of BILBO FF with Soft-Error-Tolerant Capability.

Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2011

2010

Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing.

Kazuteru Namba, Takashi Ikeda, Hideo Ito

IEEE Trans. Very Large Scale Integr. Syst., 2010

Single-Event-Upset Tolerant RS Flip-Flop with Small Area.

Kazuteru Namba, Kengo Nakashima, Hideo Ito

IEICE Trans. Inf. Syst., 2010

Chiba Scan Delay Fault Testing with Short Test Application Time.

Kazuteru Namba, Hideo Ito

J. Electron. Test., 2010

Quantitative Evaluation of Integrity for Remote System Using the Internet.

Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito

Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

Single Event Induced Double Node Upset Tolerant Latch.

Kazuteru Namba, Masatoshi Sakata, Hideo Ito

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Soft Error Tolerant BILBO FF.

Kazuteru Namba, Hideo Ito

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit.

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability.

Shuangyu Ruan, Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2009

Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits.

Kazuteru Namba, Hideo Ito

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding.

Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2009

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths.

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2009

Design for Delay Fault Testability of 2-Rail Logic Circuits.

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2009

Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding.

Kazuteru Namba, Yoshikazu Matsui, Hideo Ito

J. Electron. Test., 2009

Dependability Evaluation for Internet-Based Remote Systems.

Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Testing of Switch Blocks in Three-Dimensional FPGA.

Takumi Hoshi, Kazuteru Namba, Hideo Ito

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

A Delay Measurement Technique Using Signature Registers.

Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Connectivity of Generalized Hierarchical Completely-Connected Networks.

Toshinori Takabatake, Tomoki Nakamigawa, Hideo Ito

J. Interconnect. Networks, 2008

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

IPSJ Trans. Syst. LSI Des. Methodol., 2008

A Checkpointing Method with Small Checkpoint Latency.

Masato Kitakami, Bochuan Cai, Hideo Ito

IEICE Trans. Inf. Syst., 2008

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.

Yoichi Sasaki, Kazuteru Namba, Hideo Ito

J. Electron. Test., 2008

Path Delay Fault Test Set for Two-Rail Logic Circuits.

Kazuteru Namba, Hideo Ito

Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008

Soft Error Hardened FF Capable of Detecting Wide Error Pulse.

Shuangyu Ruan, Kazuteru Namba, Hideo Ito

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Delay Fault Testability on Two-Rail Logic Circuits.

Kazuteru Namba, Hideo Ito

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2007

Low-Cost IP Core Test Using Tri-Template-Based Codes.

Gang Zeng, Hideo Ito

IEICE Trans. Inf. Syst., 2007

Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing.

Takashi Ikeda, Kazuteru Namba, Hideo Ito

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability.

Abderrahim Doumar, Kentaroh Katoh, Hideo Ito

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006

Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree.

Gang Zeng, Hideo Ito

IEICE Trans. Inf. Syst., 2006

Redundant Design for Wallace Multiplier.

Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2006

Proposal of Testable Multi-Context FPGA Architecture.

Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2006

Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.

Kentaroh Katoh, Hideo Ito

Proceedings of the 11th European Test Symposium, 2006

Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters.

Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.

Yoichi Sasaki, Kazuteru Namba, Hideo Ito

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Concurrent core test for SOC using shared test set and scan chain disable.

Gang Zeng, Hideo Ito

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding.

Kazuteru Namba, Hideo Ito

Proceedings of the 15th Asian Test Symposium, 2006

2005

X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability.

Gang Zeng, Hideo Ito

IEICE Trans. Inf. Syst., 2005

Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core.

Gang Zeng, Hideo Ito

IEICE Trans. Inf. Syst., 2005

Scan Design for Two-Pattern Test without Extra Latches.

Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2005

Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation.

Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2005

Design of Defect Tolerant Wallace Multiplier.

Kazuteru Namba, Hideo Ito

Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift.

Kentaroh Katoh, Abderrahim Doumar, Hideo Ito

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree.

Gang Zeng, Hideo Ito

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004

Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core.

Gang Zeng, Hideo Ito

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Fault-Tolerant Message Switching Based on Wormhole Switching and Backtracking.

Manabu Sueishi, Masato Kitakami, Hideo Ito

Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

Non-Intrusive Test Compression for SOC Using Embedded FPGA Core.

Gang Zeng, Hideo Ito

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003

Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey.

Abderrahim Doumar, Hideo Ito

IEEE Trans. Very Large Scale Integr. Syst., 2003

Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core.

Gang Zeng, Hideo Ito

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks.

Toshinori Takabatake, Masato Kitakami, Hideo Ito

Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

A Fault-tolerant Routing Strategy for Generalized Hierarchical Completely-connected Networks.

Toshinori Takabatake, Masato Kitakami, Hideo Ito

Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Optimal Seed Generation for Delay Fault Detection BIST.

Lihong Tong, Kazuki Suzuki, Hideo Ito

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks.

Toshinori Takabatake, Masato Kitakami, Hideo Ito

Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Fault-Tolerance of Functional Programs Based on the Parallel Graph Reduction.

Masato Kitakami, Shunji Kubota, Hideo Ito

Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

2000

Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources.

Abderrahim Doumar, Hideo Ito

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

Testing approach within FPGA-based fault tolerant systems.

Abderrahim Doumar, Hideo Ito

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

LLT and LTn Schemes: Error Recovery Schemes in Mobile Environments.

Mikio Yagi, Keiichi Kaneko, Hideo Ito

Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999

An Automatic Testing and Diagnosis for FPGAs.

Abderrahim Doumar, Hideo Ito

Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999

Generalized Hierarchical Completely-Connected Networks.

Toshinori Takabatake, Keiichi Kaneko, Hideo Ito

Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

Fault-Tolerant Routing Algorithms for Hypercube Networks.

Keiichi Kaneko, Hideo Ito

Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

Design of an automatic testing for FPGAs.

Abderrahim Doumar, Toshiaki Ohmameuda, Hideo Ito

Proceedings of the 4th European Test Workshop, 1999

Defect and Fault Tolerance FPGAs by Shifting the Configuration Data.

Abderrahim Doumar, Satoshi Kaneko, Hideo Ito

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Testing the Logic Cells and Interconnect Resources for FPGAs.

Abderrahim Doumar, Hideo Ito

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Improving the Performance of Feedforward Neural Networks by Noise Injection into Hidden Neurons.

Hammadi Nait-Charif, Hideo Ito

J. Intell. Robotic Syst., 1998

1994

Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks.

Hideo Ito, Takashi Yagi

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993

A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube.

Hideo Ito

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1991

A hypercube design on wafer-scale integration.

Hideo Ito, Nobuyuki Suzuki

Syst. Comput. Jpn., 1991