Hideo Fujiwara

IEICE Trans. Inf. Syst., 2020

2019

A Test Generation Method Based on k-Cycle Testing for Finite State Machines.

[BibT_eX]

[DOI]

Yuya Kinoshita

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018

Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

2017

Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2017

2016

Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2016

Properties of Generalized Feedback Shift Registers for Secure Scan Design.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2016

A unified test and fault-tolerant multicast solution for network-on-chip designs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

A scheduling method for hierarchical testability based on test environment generation results.

[BibT_eX]

[DOI]

Jun Nishimaki

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2015

One More Class of Sequential Circuits having Combinational Test Generation Complexity.

[BibT_eX]

[DOI]

J. Electron. Test., 2015

A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2013

Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2013

Generalized Feed Forward Shift Registers and Their Application to Secure Scan Design.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2013

Thermal-aware test scheduling for NOC-based 3D integrated circuits.

[BibT_eX]

[DOI]

Gang Liu

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

2012

A Failure Prediction Strategy for Transistor Aging.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Test Pattern Ordering and Selection for High Quality Test Set under Constraints.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2012

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

2011

F-Scan: A DFT Method for Functional Scan at RTL.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2011

Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2011

A New Design-for-Testability Method Based on Thru-Testability.

[BibT_eX]

[DOI]

J. Electron. Test., 2011

Balanced Secure Scan: Partial Scan Approach for Secret Information Protection.

[BibT_eX]

[DOI]

J. Electron. Test., 2011

Faster-than-at-speed test for increased test quality and in-field reliability.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

Temperature-Variation-Aware Test Pattern Optimization.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Secure scan design using shift register equivalents against differential behavior attack.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Design and Optimization of Transparency-Based TAM for SoC Test.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2010

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification.

[BibT_eX]

[DOI]

Hiroshi Iwata

IEICE Trans. Inf. Syst., 2010

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint.

[BibT_eX]

[DOI]

Ryoichi Inoue

IEICE Trans. Inf. Syst., 2010

RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences.

[BibT_eX]

[DOI]

Hongxia Fang

J. Electron. Test., 2010

Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

On Minimization of Test Application Time for RAS.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage.

[BibT_eX]

[DOI]

Alodeep Sanyal

Mahmut Yilmaz

Proceedings of the 2011 IEEE International Test Conference, 2010

Constrained ATPG for functional RTL circuits using F-Scan.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Aging test strategy and adaptive test scheduling for SoC failure prediction.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Graph theoretic approach for scan cell reordering to minimize peak shift power.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Test pattern selection to optimize delay test quality with a limited size of test set.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Enabling False Path Identification from RTL for Reducing Design and Test Futileness.

[BibT_eX]

[DOI]

Hiroshi Iwata

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

A synthesis method to propagate false path information from RTL to gate level.

[BibT_eX]

[DOI]

Hiroshi Iwata

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Seed Ordering and Selection for High Quality Delay Test.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Secure and testable scan design using extended de Bruijn graphs.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms.

[BibT_eX]

[DOI]

Tsuyoshi Suzuki

Proceedings of the Distributed Computing, 23rd International Symposium, 2009

A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Partial Scan Approach for Secret Information Protection.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE European Test Symposium, 2009

Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Fast false path identification based on functional unsensitizability using RTL information.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST.

[BibT_eX]

[DOI]

Yang Zhao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2008

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2008

Test Scheduling for Multi-Clock Domain SoCs under Power Constraint.

[BibT_eX]

[DOI]

Kimihiko Masuda

IEICE Trans. Inf. Syst., 2008

Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2008

Scheduling Power-Constrained Tests through the SoC Functional Bus.

[BibT_eX]

[DOI]

Alex Orailoglu

IEICE Trans. Inf. Syst., 2008

NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2008

On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2008

Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Untestable Fault Identification in Sequential Circuits Using Model-Checking.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint.

[BibT_eX]

[DOI]

Ryoichi Inoue

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Localized random access scan: Towards low area and routing overhead.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture.

[BibT_eX]

[DOI]

Kaiwei Li

Krishnaiyan Thulasiraman

Jiaguang Sun

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST.

[BibT_eX]

[DOI]

Mingjing Chen

IEEE Trans. Computers, 2007

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation.

[BibT_eX]

[DOI]

Thomas Clouqueur

IEICE Trans. Inf. Syst., 2007

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2007

Functional Constraints vs. Test Compression in Scan-Based Delay Testing.

[BibT_eX]

[DOI]

Ilia Polian

J. Electron. Test., 2007

Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

TAM Design and Optimization for Transparency-Based SoC Test.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Fast and effective fault simulation for path delay faults based on selected testable paths.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Efficient path delay test generation based on stuck-at test generation using checker circuitry.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints.

[BibT_eX]

[DOI]

Proceedings of the 12th European Test Symposium, 2007

Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers.

[BibT_eX]

[DOI]

Masahiro Imanishi

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A DFT Method for Time Expansion Model at Register Transfer Level.

[BibT_eX]

[DOI]

Hiroyuki Iwata

Proceedings of the 44th Design Automation Conference, 2007

Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE.

[BibT_eX]

[DOI]

Dan Zhao

Ronghua Huang

Proceedings of the 16th Asian Test Symposium, 2007

Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults.

[BibT_eX]

[DOI]

Yuki Yoshikawa

Proceedings of the 16th Asian Test Symposium, 2007

Test Scheduling for Memory Cores with Built-In Self-Repair.

[BibT_eX]

[DOI]

Yuusuke Fukuda

Proceedings of the 16th Asian Test Symposium, 2007

Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost.

[BibT_eX]

[DOI]

Dianwei Hu

Proceedings of the 16th Asian Test Symposium, 2007

Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Fault-dependent/independent Test Generation Methods for State Observable FSMs.

[BibT_eX]

[DOI]

Ryoichi Inoue

Proceedings of the 16th Asian Test Symposium, 2007

Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores.

[BibT_eX]

[DOI]

Dan Zhao

Unni Chandran

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.

[BibT_eX]

[DOI]

Alex Orailoglu

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

System-on-chip test scheduling with reconfigurable core wrappers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Design for consecutive transparency method of RTL circuits.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 2006

A Low Power Deterministic Test Using Scan Chain Disable Technique.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2006

Effect of BIST Pretest on IC Defect Level.

[BibT_eX]

[DOI]

Yoshiyuki Nakamura

Jacob Savir

IEICE Trans. Inf. Syst., 2006

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2006

A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips.

[BibT_eX]

[DOI]

Masahide Miyazaki

IEICE Trans. Inf. Syst., 2006

BIST Pretest of ICs: Risks and Benefits.

[BibT_eX]

[DOI]

Yoshiyuki Nakamura

Jacob Savir

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A New Class of Sequential Circuits with Acyclic Test Generation Complexity.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Power-Constrained SOC Test Schedules through Utilization of Functional Buses.

[BibT_eX]

[DOI]

Alex Orailoglu

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Low-Cost Hardening of Image Processing Applications Against Soft Errors.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Electrical Behavior of GOS Fault affected Domino Logic Cell.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Power-constrained test scheduling for multi-clock domain SoCs.

[BibT_eX]

[DOI]

Kimihiko Masuda

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A New Scan Design Technique Based on Pre-Synthesis Thru Functions.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

Design for Testability of Software-Based Self-Test for Processors.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture.

[BibT_eX]

[DOI]

Jiaguang Sun

Yang Zhao

Proceedings of the 15th Asian Test Symposium, 2006

A memory grouping method for sharing memory BIST logic.

[BibT_eX]

[DOI]

Masahide Miyazaki

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Improving test effectiveness of scan-based BIST by scan chain partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Delay Fault Testing of Processor Cores in Functional Mode.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Classification of Sequential Circuits Based on tauk Notation and Its Applications.

[BibT_eX]

[DOI]

Thomas Clouqueur

IEICE Trans. Inf. Syst., 2005

Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST.

[BibT_eX]

[DOI]

Yoshiyuki Nakamura

Jacob Savir

IEICE Trans. Inf. Syst., 2005

Design and analysis of multiple weight linear compactors of responses containing unknown values.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Instruction-based delay fault self-testing of pipelined processor cores.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Testing Superscalar Processors in Functional Mode.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

Design for Testability Based on Single-Port-Change Delay Testing for Data Paths.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability.

[BibT_eX]

[DOI]

Hisakazu Takakuwa

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops.

[BibT_eX]

[DOI]

Kaiwei Li

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST.

[BibT_eX]

[DOI]

Ming-Jing Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Efficient Constraint Extraction for Template-Based Processor Self-Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

An Effective Design for Hierarchical Test Generation Based on Strong Testability.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A Class of Linear Space Compactors for Enhanced Diagnostic.

[BibT_eX]

[DOI]

Thomas Clouqueur

Kewal K. Saluja

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Efficient test solutions for core-based designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A DFT Selection Method for Reducing Test Application Time of System-on-Chips.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2004

Preemptive System-on-Chip Test Scheduling.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2004

New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency.

[BibT_eX]

[DOI]

J. Electron. Test., 2004

Design & Test Education in Asia.

[BibT_eX]

IEEE Des. Test Comput., 2004

Instruction-Based Delay Fault Self-Testing of Processor Cores.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A design methodology to realize delay testable controllers using state transition information.

[BibT_eX]

[DOI]

Proceedings of the 9th European Test Symposium, 2004

An efficient scan tree design for test time reduction.

[BibT_eX]

[DOI]

Proceedings of the 9th European Test Symposium, 2004

Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Classification of Sequential Circuits Based on ?k Notation.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Efficient Template Generation for Instruction-Based Self-Test of Processor Cores.

[BibT_eX]

[DOI]

Kazuko Kambe

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution.

[BibT_eX]

[DOI]

Yi Xu

IEEE Trans. Computers, 2003

Design for Consecutive Transparency of Cores in System-on-a-Chip.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Test Resource Partitioning and Optimization for SOC Designs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability.

[BibT_eX]

[DOI]

Tetsuo Uchiyama

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms.

[BibT_eX]

[DOI]

Kouhei Ohtani

Proceedings of the 2003 Design, 2003

Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis.

[BibT_eX]

[DOI]

Shan Gu

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Software-Based Delay Fault Testing of Processor Cores.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Optimal System-on-Chip Test Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Test Synthesis for Datapaths Using Datapath-Controller Functions.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Handling the pin overhead problem of DFTs for high-quality and at-speed tests.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

SPIRIT: a highly robust combinational test generation algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A nonscan DFT method for controllers to provide complete fault efficiency.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 2002

Parallel algorithms for selection on the BSP and BSP* models.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 2002

Test sequence compaction methods for acyclic sequential circuits using a time expansion model.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 2002

A layout adjustment problem for disjoint rectangles preserving orthogonal order.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 2002

A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2002

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits.

[BibT_eX]

[DOI]

Shunjiro Miwa

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

An Extended Class of Sequential Circuits with Combinational Test Generation Complexity.

[BibT_eX]

[DOI]

Chikateru Jinno

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Power constrained preemptive TAM scheduling.

[BibT_eX]

[DOI]

Proceedings of the 7th European Test Workshop, 2002

Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis.

[BibT_eX]

[DOI]

Shan Gu

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Integrated Test Scheduling, Test Parallelization and TAMDesign.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Fault Set Partition for Efficient Width Compression.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Design for Two-Pattern Testability of Controller-Data Path Circuits.

[BibT_eX]

[DOI]

Atlaf Ul Amin

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

A causal broadcast protocol for distributed mobile systems.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 2001

Adaptive Long-Lived O(k2)-Renaming with O(k2) Steps.

[BibT_eX]

[DOI]

Proceedings of the Distributed Computing, 15th International Conference, 2001

Testable Design of Sequential Circuits with Improved Fault Efficiency.

[BibT_eX]

[DOI]

Bhargab B. Bhattacharya

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

A Framework for Low Complexity Static Learning.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Design for Hierarchical Two-Pattern Testability of Data Paths.

[BibT_eX]

[DOI]

Md. Altaf-Ul-Amin

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

A New Class of Sequential Circuits with Combinational Test Generation Complexity.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

LFSR-Based Deterministic TPG for Two-Pattern Testing.

[BibT_eX]

[DOI]

Xiaowei Li

Paul Y. S. Cheung

J. Electron. Test., 2000

Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Non-scan design for testability for synchronous sequential circuits based on conflict analysis.

[BibT_eX]

[DOI]

Yi Xu

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Test Generation for Acyclic Sequential Circuits with Hold Registers.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Single-control testability of RTL data paths for BIST.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Strong self-testability for data paths high-level synthesis.

[BibT_eX]

[DOI]

Xiaowei Li

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A class of sequential circuits with combinational test generation complexity under single-fault assumption.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Spirit: satisfiability problem implementation for redundancy identification and test generation.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A non-scan DFT method at register-transfer level to achieve complete fault efficiency.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

A cost optimal parallel algorithm for weighted distance transforms.

[BibT_eX]

[DOI]

Parallel Comput., 1999

Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure.

[BibT_eX]

[DOI]

Tomoya Takasaki

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description.

[BibT_eX]

[DOI]

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model.

[BibT_eX]

[DOI]

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency.

[BibT_eX]

[DOI]

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

On the synthesis of synchronizable finite state machines with partial scan.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 1998

Partial scan design methods based on internally balanced structure.

[BibT_eX]

[DOI]

Tomoya Takasaki

Syst. Comput. Jpn., 1998

An approach to test synthesis from higher level.

[BibT_eX]

[DOI]

Integr., 1998

Universal Fault Diagnosis for Lookup Table FPGAs.

[BibT_eX]

[DOI]

Satoshi Miyazaki

IEEE Des. Test Comput., 1998

Needed: Third-generation ATPG Benchmarks.

[BibT_eX]

IEEE Des. Test Comput., 1998

SelfStabilizing WaitFree Clock Synchronization with Bounded Space.

[BibT_eX]

Proceedings of the Distributed Computing, 1998

A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency.

[BibT_eX]

[DOI]

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

A High-Level Synthesis Method for Weakly Testable Data Paths.

[BibT_eX]

[DOI]

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits.

[BibT_eX]

[DOI]

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Fault-tolerant distributed algorithms for autonomous mobile robots with crash faults.

[BibT_eX]

[DOI]

Daisuke Yoshida

Syst. Comput. Jpn., 1997

Non-scan design for testable data paths using thru operation.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 1997

A sequential circuit structure with combinational test generation complexity and its application.

[BibT_eX]

[DOI]

Tomoya Takasaki

Syst. Comput. Jpn., 1997

Parallel algorithms for connected-component problems of gray-scale images.

[BibT_eX]

[DOI]

Akihiro Fujiwara

Syst. Comput. Jpn., 1997

A latency-optimal superstabilizing mutual exclusion protocol.

[BibT_eX]

Proceedings of the 3rd Workshop on Self-stabilizing Systems, 1997

Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System.

[BibT_eX]

[DOI]

Proceedings of the Distributed Algorithms, 11th International Workshop, 1997

A Parallel Algorithm for Weighted Distance Transforms.

[BibT_eX]

[DOI]

Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

Sequential Test Generation Based on Circuit Pseudo-Transformation.

[BibT_eX]

[DOI]

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Testing for the programming circuit of LUT-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs.

[BibT_eX]

[DOI]

Satoshi Miyazaki

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

A Snapshot Algorithm for Distributed Mobile Systems.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Distributed Computing Systems, 1996

A Test Methodology for Interconnect Structures of LUT-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan.

[BibT_eX]

[DOI]

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Optimal Granularity and Scheme of Parallel Test Generation in a Distributed System.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1995

An Optimal Parallel Algorithm for the Euclidean Distance Maps of 2-D Binary Images.

[BibT_eX]

[DOI]

Akihiro Fujiwara

Inf. Process. Lett., 1995

Foreword.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 1995

A scheduling problem in test generation.

[BibT_eX]

[DOI]

Hironori Maeda

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Universal test complexity of field-programmable gate arrays.

[BibT_eX]

[DOI]

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

A method of search space pruning based on search state dominance.

[BibT_eX]

[DOI]

Takayuki Fujino

Syst. Comput. Jpn., 1994

1993

Parity-scan design to reduce the cost of test application.

[BibT_eX]

[DOI]

Akihiro Yamamoto

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

A Search Space Pruning Method for Test Pattern Generation using Search State Dominance.

[BibT_eX]

[DOI]

Takayuki Fujino

J. Circuits Syst. Comput., 1993

1992

An Efficient Test Generation Algorithm Based on Search State Dominance.

[BibT_eX]

[DOI]

Takayuki Fujino

Proceedings of the Digest of Papers: FTCS-22, 1992

1990

Optimal granularity of test generation in a distributed system.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Computational Complexity of Controllability/Observability Problems for Combinational Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1990

Three-valued neural networks for test generation.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

1989

Enhancing random-pattern coverage of programmable logic arrays via masking technique.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988

A design of programmable logic arrays with random pattern-testability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Test research in Japan.

[BibT_eX]

[DOI]

IEEE Des. Test, 1988

Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique.

[BibT_eX]

[DOI]

Osamu Fujisawa

Kazunori Hikone

Proceedings of the Proceedings International Test Conference 1988, 1988

1987

A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead.

[BibT_eX]

[DOI]

Robert P. Treuer

Vinod K. Agarwal

IEEE Trans. Computers, 1987

A random-pattern testable design for programmable logic arrays.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 1987

1986

Design for testability and built-in self-test for VLSI circuits.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 1986

1985

Implementing a Built-In Self-Test PLA Design.

[BibT_eX]

[DOI]

Robert P. Treuer

Vinod K. Agarwal

IEEE Des. Test, 1985

A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead.

[BibT_eX]

Kewal K. Saluja

Proceedings of the Proceedings International Test Conference 1985, 1985

1984

A New PLA Design for Universal Testability.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1984

Design for Testability for Complete Test Coverage.

[BibT_eX]

[DOI]

Akira Motohara

IEEE Des. Test, 1984

1983

An Easily Testable Design of Programmable Logic Arrays for Multiple Faults.

[BibT_eX]

[DOI]

Kewal K. Saluja

IEEE Trans. Computers, 1983

On the Acceleration of Test Generation Algorithms.

[BibT_eX]

[DOI]

Takeshi Shimono

IEEE Trans. Computers, 1983

Test generation for scan design circuits with tri-state modules and bidirectional terminals.

[BibT_eX]

[DOI]

Proceedings of the 20th Design Automation Conference, 1983

1982

The Complexity of Fault Detection Problems for Combinational Logic Circuits.

[BibT_eX]

[DOI]

Shunichi Toida

IEEE Trans. Computers, 1982

1981

A Design of Programmable Logic Arrays with Universal Tests.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1981

On Closedness and Test Complexity of Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1981

1978

Some Existence Theorems for Probabilistically Diagnosable Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1978

Connection Assignments for Probabilistically Diagnosable Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1978

On the Computational Complexity of System Diagnosis.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1978

LORES - Logic Reorganization System.

[BibT_eX]

[DOI]

Proceedings of the 15th Design Automation Conference, 1978

1975

Easily Testable Sequential Machines with Extra Inputs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1975

1974

Design of Diagnosable Sequential Machines Utilizing Extra Outputs.

[BibT_eX]

[DOI]