Hidenobu Miyamoto
According to our database1,
Hidenobu Miyamoto
authored at least 4 papers
between 1992 and 2000.
Collaborative distances:
Collaborative distances:
Timeline
1992
1993
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1995
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1998
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2000
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2000
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme.
IEEE J. Solid State Circuits, 2000
1999
IEEE J. Solid State Circuits, 1999
1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1992
IEEE J. Solid State Circuits, November, 1992