Hidenobu Miyamoto

According to our database1, Hidenobu Miyamoto authored at least 4 papers between 1992 and 2000.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1992
1993
1994
1995
1996
1997
1998
1999
2000
0
1
2
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2000
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme.
IEEE J. Solid State Circuits, 2000

1999
A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications.
IEEE J. Solid State Circuits, 1999

1998
An embedded FeRAM macro cell for a smart card microcontroller.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1992
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function.
IEEE J. Solid State Circuits, November, 1992


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