Hidenobu Miyamoto

According to our database, Hidenobu Miyamoto authored at least 3 papers between 1998 and 2000.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2000

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme.

Yasuhiro Takai, Mamoru Fujita, Kyoichi Nagata, Satoshi Isa, Shigeyuki Nakazawa, Atsunori Hirobe, Hiroaki Ohkubo, Masato Sakao, Shinichi Horiba, Tadashi Fukase, Yoshihiro Takaishi, Makoto Matsuo, Masahiro Komuro, Tetsuya Uchida, Takashi Sakoh, Kanta Saino, Shirou Uchiyama, Yuichi Takada, Junichi Sekine, Nobuko Nakanishi, Takeshi Oikawa, Masahiko Igeta, Hiroyoshi Tanabe, Hidenobu Miyamoto, Takeo Hashimoto, Hiromu Yamaguchi, Kuniaki Koyama, Yasuo Kobayashi, Takashi Okuda

IEEE J. Solid State Circuits, 2000

1999

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications.

Muneo Fukaishi, Satoshi Nakamura, Akio Tajima, Yasushi Kinoshita, Yoshihiko Suemura, Hisamitsu Suzuki, Toshiro Itani, Hidenobu Miyamoto, Naoya Henmi, Tohru Yamazaki, Michio Yotsuyanagi

IEEE J. Solid State Circuits, 1999

1998

An embedded FeRAM macro cell for a smart card microcontroller.

Tohru Miwa, Junichi Yamada, Yuji Okamoto, Hiroki Koike, Hideo Toyoshiina, Hiromitsu Hada, Yoshihiro Hayashi, Hiroaki Oliizaki, Yoichi Miyasalca, Takemitsu Kunio, Hidenobu Miyamoto, Hideki Gomi, Hiroshi Kitajima

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998