Hidenari Nakashima

According to our database1, Hidenari Nakashima authored at least 10 papers between 2004 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2010
Impact of Self-Heating in Wire Interconnection on Timing.
IEICE Trans. Electron., 2010

2009
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2007
Proposal of Metrics for SSTA Accuracy Evaluation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Fast Methods to Estimate Clock Jitter due to Power Supply Noise.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2005
Evaluation of X Architecture Using Interconnect Length Distribution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Wire Length Distribution Model for System LSI.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Wire Length Distribution Model Considering Core Utilization for System on Chip.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

2004
ULSI Interconnect Length Distribution Model Considering Core Utilization.
Proceedings of the 2004 Design, 2004


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