Hideki Osone
According to our database1,
Hideki Osone
authored at least 6 papers
between 1995 and 2011.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2011
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2009
A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control.
IEEE J. Solid State Circuits, 2009
A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2007
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
1995
Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System.
Proceedings of the Digest of Papers: FTCS-25, 1995