Hideki Kano
According to our database1,
Hideki Kano
authored at least 8 papers
between 1998 and 2016.
Collaborative distances:
Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2016
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE.
IEEE J. Solid State Circuits, 2014
3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2002
IEEE J. Solid State Circuits, 2002
1998
IEEE J. Solid State Circuits, 1998