Hidekazu Terai

According to our database, Hidekazu Terai authored at least 27 papers between 1983 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

Dedicated Hardware for Ant Colony Optimization Using Distributed Memory.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

OX Hardware Engine for High Speed Character Inheritance.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the 2009 International Conference on Genetic and Evolutionary Methods, 2009

Car Navigation System Based on Hybrid Genetic Algorithm.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008

Hybrid Architecture of Genetic Algorithm and Simulated Annealing.

Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Terai

Eng. Lett., 2008

Route selection algorithm based on integer operation Ant Colony Optimization.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the IEEE International Conference on Information Reuse and Integration, 2008

Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the 2008 International Conference on Genetic and Evolutionary Methods, 2008

2007

Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption.

Masaya Yoshikawa, Hidekazu Terai

J. Adv. Comput. Intell. Intell. Informatics, 2007

The new DFM approach based on a genetic algorithm.

Masaya Yoshikawa, Hidekazu Terai

Artif. Life Robotics, 2007

Architecture for high-speed Ant Colony Optimization.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the IEEE International Conference on Information Reuse and Integration, 2007

2006

Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation.

Masaya Yoshikawa, Hidekazu Terai

J. Adv. Comput. Intell. Intell. Informatics, 2006

Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the Fourth International Conference on Software Engineering, 2006

Immune Algorithm Processor.

Masaya Yoshikawa, Masahiro Fukui, Hidekazu Terai

Proceedings of the 21st International Conference on Computers and Their Applications, 2006

Co-evolutionary robotics using two kinds of neural networks.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the ISCA 19th International Conference on Computer Applications in Industry and Engineering, 2006

2005

Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the Third ACIS International Conference on Software Engineering, 2005

A Hierarchical Parallel Placement Technique based on Genetic Algorithm.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the Fifth International Conference on Intelligent Systems Design and Applications (ISDA 2005), 2005

Hybrid genetic algorithm engine for high-speed floorplanning.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Performance driven placement technique based on collaboration of software and hardware.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the IEEE Congress on Evolutionary Computation, 2005

2004

VLSI processor architecture for real-time GA processing and PE-VLSI design.

Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002

Scalable GA processor architecture and its implementation of processor-element.

Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi

Proceedings of the IEEE International Conference on Acoustics, 2002

1994

Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1.

Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno

Proceedings of the 31st Conference on Design Automation, 1994

1991

Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers.

Hidekazu Terai, Fumio Goto, Katsuro Wakai, Tokinori Kozawa, Mitsugu Edagawa, Satoshi Hososaka, Masahiro Hashimoto

Proceedings of the 28th Design Automation Conference, 1991

1988

Automatic Layout Procedures for Serial Routing Devices.

Yasushi Ogawa, Hidekazu Terai, Tokinori Kozawa

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1986

Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs.

Yasushi Ogawa, Tatsuki Ishii, Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, Kyoji Yuyama, Kyoji Chiba

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985

Research in Design Automation for VLSI Layout.

Tokinori Kozawa, Hidekazu Terai

IEEE Des. Test, 1985

A routing procedure for mixed array of custom macros and standard cells.

Hidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

Combine and top down block placement algorithm for hierarchical logic VLSI layout.

Tokinori Kozawa, Chihei Miura, Hidekazu Terai

Proceedings of the 21st Design Automation Conference, 1984

1983

Automatic placement algorithms for high packing density V L S I.

Tokinori Kozawa, Hidekazu Terai, Tatsuki Ishii, Michiyoshi Hayase, Chihei Miura, Yasushi Ogawa, Kuniaki Kishida, Norio Yamada, Yasuhiro Ohno

Proceedings of the 20th Design Automation Conference, 1983