Hidehiro Takata
According to our database1,
Hidehiro Takata
authored at least 23 papers
between 1988 and 2015.
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Bibliography
2015
An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2012
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEICE Trans. Electron., 2012
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction.
IEICE Trans. Electron., 2012
2011
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch.
IEICE Trans. Electron., 2011
On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling.
ACM Trans. Design Autom. Electr. Syst., 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
2009
Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations.
IEICE Trans. Electron., 2009
2008
Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling.
Proceedings of the 45th Design Automation Conference, 2008
2007
Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS.
IEICE Trans. Electron., 2007
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2005
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2002
A 99-mm<sup>2</sup> 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system.
IEEE J. Solid State Circuits, 2002
2001
A 99-mm<sup>2</sup>, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
1999
A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor.
IEEE J. Solid State Circuits, 1999
1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1989
IEEE J. Solid State Circuits, October, 1989
IEEE J. Solid State Circuits, August, 1989
1988
IEEE J. Solid State Circuits, February, 1988