Hideaki Yamamoto

Orcid: 0000-0003-3362-5376

According to our database1, Hideaki Yamamoto authored at least 13 papers between 2000 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation.
Proceedings of the International Joint Conference on Neural Networks, 2022

2021
Computational Efficiency of a Modular Reservoir Network for Image Recognition.
Frontiers Comput. Neurosci., 2021

A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2021, 2021

2020
Contribution of AMPA and NMDA receptors in the spontaneous firing patterns of single neurons in autaptic culture.
Biosyst., 2020

2019
Quantitative Analysis of Dynamical Complexity in Cultured Neuronal Network Models for Reservoir Computing Applications.
Proceedings of the International Joint Conference on Neural Networks, 2019

2018
Effective Subnetwork Topology for Synchronizing Interconnected Networks of Coupled Phase Oscillators.
Frontiers Comput. Neurosci., 2018

2017
Control of the Correlation of Spontaneous Neuron Activity in Biological and Noise-activated CMOS Artificial Neural Microcircuits.
CoRR, 2017

Modularity-dependent modulation of synchronized bursting activity in cultured neuronal network models.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

2011
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.
IEEE J. Solid State Circuits, 2011

2010
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Ultra-Small Reader/Writer with Multiple Contactless Interfaces on a Flexible Circuit Board.
IEICE Trans. Commun., 2009

2000
A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM.
IEEE J. Solid State Circuits, 2000

A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


  Loading...