Hervé Naudet
According to our database1,
Hervé Naudet
authored at least 5 papers
between 2012 and 2016.
Collaborative distances:
Collaborative distances:
Timeline
2012
2013
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2015
2016
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Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2016
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs.
J. Electron. Test., 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
2012
Proceedings of the 17th IEEE European Test Symposium, 2012