Herschel A. Ainspan
According to our database1,
Herschel A. Ainspan
authored at least 50 papers
between 1995 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1\mathrm{V}_{\text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2022
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2020
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.
IEEE J. Solid State Circuits, 2020
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020
2019
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2012
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects.
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2009
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback.
IEEE J. Solid State Circuits, 2007
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
IEEE J. Solid State Circuits, 2005
2003
IEEE J. Solid State Circuits, 2003
IBM J. Res. Dev., 2003
IBM J. Res. Dev., 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2000
SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems.
IEEE J. Solid State Circuits, 2000
1999
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
IEEE J. Solid State Circuits, 1998
IEEE J. Solid State Circuits, 1998
1997
IEEE J. Solid State Circuits, 1997
1996
IEEE J. Solid State Circuits, 1996
1995
Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier.
IBM J. Res. Dev., 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995