Henry Samueli

According to our database1, Henry Samueli authored at least 32 papers between 1989 and 2001.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2000, "For contributions to VLSI architectures and realizations for high-bit rate digital communication systems.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2001
A frequency-agile single-chip QAM modulator with beamforming diversity.
IEEE J. Solid State Circuits, 2001

2000
Analysis and design of a frequency-hopped spread-spectrum transceiver for wireless personal communications.
IEEE Trans. Veh. Technol., 2000

The Broadband Revolution.
IEEE Micro, 2000

Field trial results for high-speed wireless indoor data communications.
IEEE J. Sel. Areas Commun., 2000

Embedded systems design in the new millennium (panel session).
Proceedings of the 37th Conference on Design Automation, 2000

A single-chip universal burst receiver for cable modem/digital cable-TV applications.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

A 8.75-MBaud single-chip digital QAM modulator with frequency-agility and beamforming diversity.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
Correction to "A 70-Mb/s Variable-Rate 1024-QAM Cable Receiver IC with Integrated 10-b ADC and FEC Decoder".
IEEE J. Solid State Circuits, 1999

A single-chip universal digital satellite receiver with 480-MHz IF input.
IEEE J. Solid State Circuits, 1999

A single-chip universal cable set-top box/modem transceiver.
IEEE J. Solid State Circuits, 1999

Adaptive antenna arrays and equalization techniques for high bit-rate QAM receivers.
IEEE J. Sel. Areas Commun., 1999

1998
A 70-Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10-b ADC and FEC decoder.
IEEE J. Solid State Circuits, 1998

A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS. II. Receiver design.
IEEE J. Solid State Circuits, 1998

A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS. I. Architecture and transmitter design.
IEEE J. Solid State Circuits, 1998

A digital adaptive beamforming QAM demodulator IC for high bit-rate wireless communications.
IEEE J. Solid State Circuits, 1998

Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

A dual-channel QAM/QPSK receiver IC with integrated cable set-top box functionality.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1996
A low-power baseband receiver IC for frequency-hopped spread spectrum communications.
IEEE J. Solid State Circuits, 1996

Design techniques for silicon compiler implementations of high-speed FIR digital filters.
IEEE J. Solid State Circuits, 1996

1995
An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 μm CMOS.
IEEE J. Solid State Circuits, December, 1995

A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS.
IEEE J. Solid State Circuits, March, 1995

A 300 MHz digital double-sideband to single-sideband converter in 1 μm CMOS.
IEEE J. Solid State Circuits, January, 1995

A 1.6 Mbps Digital-QAM System for DSL Transmission.
IEEE J. Sel. Areas Commun., 1995

1994
A single-chip 12.7 Mchips/s digital IF BPSK direct sequence spread-spectrum transceiver in 1.2 μm CMOS.
IEEE J. Solid State Circuits, December, 1994

1993
Performance Analysis of an All-Digital BPSK Direct-Sequence Spread-Spectrum IF Receiver Architecture.
IEEE J. Sel. Areas Commun., 1993

1992
DDFSGEN.
J. VLSI Signal Process., 1992

1991
The design of low-complexity in linear-phase FIR filter banks using powers-of-two coefficients with an application to subband image coding.
IEEE Trans. Circuits Syst. Video Technol., 1991

A 64-Tap CMOS Echo Canceller/Decision Feedback Equalizer for 2B1Q HDSL Transceivers.
IEEE J. Sel. Areas Commun., 1991

A VLSI architecture for a universal high-speed multirate FIR digital filter with selectable power-of-two decimation/interpolation ratios.
Proceedings of the 1991 International Conference on Acoustics, 1991

A reconfigurable decision-feedback equalizer chip set architecture for high bit-rate QAM digital modems.
Proceedings of the 1991 International Conference on Acoustics, 1991

1990
A VLSI Architecture for a High-Speed All-Digital Quadrature Modulator and Demodulator for Digital Radio Applications.
IEEE J. Sel. Areas Commun., 1990

1989
A low-complexity multiplierless half-band recursive digital filter design.
IEEE Trans. Acoust. Speech Signal Process., 1989


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