Henry Samueli
According to our database1,
Henry Samueli
authored at least 32 papers
between 1989 and 2001.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2000, "For contributions to VLSI architectures and realizations for high-bit rate digital communication systems.".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2001
IEEE J. Solid State Circuits, 2001
2000
Analysis and design of a frequency-hopped spread-spectrum transceiver for wireless personal communications.
IEEE Trans. Veh. Technol., 2000
IEEE J. Sel. Areas Commun., 2000
Proceedings of the 37th Conference on Design Automation, 2000
A single-chip universal burst receiver for cable modem/digital cable-TV applications.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
A 8.75-MBaud single-chip digital QAM modulator with frequency-agility and beamforming diversity.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
Correction to "A 70-Mb/s Variable-Rate 1024-QAM Cable Receiver IC with Integrated 10-b ADC and FEC Decoder".
IEEE J. Solid State Circuits, 1999
IEEE J. Solid State Circuits, 1999
IEEE J. Solid State Circuits, 1999
IEEE J. Sel. Areas Commun., 1999
1998
A 70-Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10-b ADC and FEC decoder.
IEEE J. Solid State Circuits, 1998
A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS. II. Receiver design.
IEEE J. Solid State Circuits, 1998
A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS. I. Architecture and transmitter design.
IEEE J. Solid State Circuits, 1998
A digital adaptive beamforming QAM demodulator IC for high bit-rate wireless communications.
IEEE J. Solid State Circuits, 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1996
A low-power baseband receiver IC for frequency-hopped spread spectrum communications.
IEEE J. Solid State Circuits, 1996
Design techniques for silicon compiler implementations of high-speed FIR digital filters.
IEEE J. Solid State Circuits, 1996
1995
An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 μm CMOS.
IEEE J. Solid State Circuits, December, 1995
IEEE J. Solid State Circuits, March, 1995
IEEE J. Solid State Circuits, January, 1995
1994
A single-chip 12.7 Mchips/s digital IF BPSK direct sequence spread-spectrum transceiver in 1.2 μm CMOS.
IEEE J. Solid State Circuits, December, 1994
1993
Performance Analysis of an All-Digital BPSK Direct-Sequence Spread-Spectrum IF Receiver Architecture.
IEEE J. Sel. Areas Commun., 1993
1992
1991
The design of low-complexity in linear-phase FIR filter banks using powers-of-two coefficients with an application to subband image coding.
IEEE Trans. Circuits Syst. Video Technol., 1991
IEEE J. Sel. Areas Commun., 1991
A VLSI architecture for a universal high-speed multirate FIR digital filter with selectable power-of-two decimation/interpolation ratios.
Proceedings of the 1991 International Conference on Acoustics, 1991
A reconfigurable decision-feedback equalizer chip set architecture for high bit-rate QAM digital modems.
Proceedings of the 1991 International Conference on Acoustics, 1991
1990
A VLSI Architecture for a High-Speed All-Digital Quadrature Modulator and Demodulator for Digital Radio Applications.
IEEE J. Sel. Areas Commun., 1990
1989
IEEE Trans. Acoust. Speech Signal Process., 1989