Henry Park

According to our database1, Henry Park authored at least 15 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021
56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Male Adolescents' and Young Adults' Evaluations of Interracial Exclusion in Offline and Online Settings.
Cyberpsychology Behav. Soc. Netw., 2019

A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016
A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016

A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014
Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

An INL Yield Model of the Digital-to-Analog Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

In Situ SRAM Static Stability Estimation in 65-nm CMOS.
IEEE J. Solid State Circuits, 2013

A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs).
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
Analysis of STT-RAM cell design with multiple MTJs per access.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011


  Loading...