Henry Lopez Davila
Orcid: 0000-0002-0534-0085
According to our database1,
Henry Lopez Davila
authored at least 9 papers
between 2015 and 2023.
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Bibliography
2023
Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2023
2020
A 75-Gb/s/mm<sup>2</sup> and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 16/64 QAM Baseband SoC for mm-Wave Transceiver with Self-Healing for FD/FI IQ Mismatch, LO Leakage and CFO/SCO/PNC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
Digital Self-Interference Cancellation for OFDM Full-Duplex Transmission in 60 GHz Band.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
2015
A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015