Henry H. Y. Chan

According to our database, Henry H. Y. Chan authored at least 5 papers between 2001 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2007

A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits.

Henry H. Y. Chan, Zeljko Zilic

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops.

Henry H. Y. Chan, Zeljko Zilic

Proceedings of the 44th Design Automation Conference, 2007

2005

Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization.

Henry H. Y. Chan, Zeljko Zilic

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004

Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach.

Henry H. Y. Chan, Zeljko Zilic

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2001

A practical substrate modeling algorithm with active guardband macromodel for mixed-signal substrate coupling verification.

Henry H. Y. Chan, Zeljko Zilic

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001