Henry Cook

According to our database, Henry Cook authored at least 16 papers between 2008 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Insights gained from constructing a large scale dynamic analysis platform.

Cody Miller, Dae Glendowne, Henry Cook, Thomas DeMarcus, Chris Lanclos, Patrick Pape

Digit. Investig., 2017

Microprocessor chip with photonic I/O.

Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael S. Georgas, Andrew S. Waterman, Jeffrey M. Shainline, Rimas R. Avizienis, Sen Lin, Benjamin R. Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry M. Cook, Albert J. Ou, Jonathan C. Leu, Yu-Hsin Chen, Krste Asanovic, Rajeev J. Ram, Milos A. Popovic, Vladimir Marko Stojanovic

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

2016

Productive Design of Extensible On-Chip Memory Hierarchies.

Henry Cook

PhD thesis, 2016

An Agile Approach to Building RISC-V Microprocessors.

Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Rimas Avizienis, Brian C. Richards, Jonathan Bachrach, David A. Patterson, Elad Alon, Bora Nikolic, Krste Asanovic

IEEE Micro, 2016

2015

Single-chip microprocessor that communicates directly using light.

Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael Georgas, Andrew Waterman, Jeffrey M. Shainline, Rimas Avizienis, Sen Lin, Benjamin Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry Cook, Albert J. Ou, Jonathan C. Leu, Yu-Hsin Chen, Krste Asanovic, Rajeev J. Ram, Milos A. Popovic, Vladimir Marko Stojanovic

Nat., 2015

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.

Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2014

A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators.

Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, Vladimir Stojanovic, Krste Asanovic

Proceedings of the ESSCIRC 2014, 2014

2013

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness.

Henry Cook, Miquel Moretó, Sarah Bird, Khanh Dao, David A. Patterson, Krste Asanovic

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

The RISC-V instruction set.

Andrew Waterman, Yunsup Lee, Rimas Avizienis, Henry Cook, David A. Patterson, Krste Asanovic

Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

2012

Portable parallel performance from sequential, productive, embedded domain-specific languages.

Shoaib Kamil, Derrick Coetzee, Scott Beamer, Henry Cook, Ekaterina Gonina, Jonathan Harper, Jeffrey Morlan, Armando Fox

Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012

2011

CudaDMA: optimizing GPU memory bandwidth via warp specialization.

Michael Bauer, Henry Cook, Brucek Khailany

Proceedings of the Conference on High Performance Computing Networking, 2011

CUDA-level Performance with Python-level Productivity for Gaussian Mixture Model Applications.

Henry Cook, Ekaterina Gonina, Shoaib Kamil, Gerald Friedland, David A. Patterson, Armando Fox

Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism, 2011

Fast speaker diarization using a high-level scripting language.

Ekaterina Gonina, Gerald Friedland, Henry Cook, Kurt Keutzer

Proceedings of the 2011 IEEE Workshop on Automatic Speech Recognition & Understanding, 2011

2010

A case for FAME: FPGA architecture model execution.

Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David A. Patterson

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

RAMP gold: an FPGA-based architecture simulator for multiprocessors.

Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanovic

Proceedings of the 47th Design Automation Conference, 2010

2008

Predictive design space exploration using genetically programmed response surfaces.

Henry Cook, Kevin Skadron

Proceedings of the 45th Design Automation Conference, 2008