Henrique Cota de Freitas
Orcid: 0000-0001-9722-1093Affiliations:
- Pontifícia Universidade Católica de Minas Gerais, Belo Horizonte, Brazil
According to our database1,
Henrique Cota de Freitas
authored at least 46 papers
between 2001 and 2024.
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Bibliography
2024
IEEE Consumer Electron. Mag., July, 2024
Expert Syst. J. Knowl. Eng., April, 2024
IEEE Access, 2024
2023
LWMPI: An MPI library for NoC-based lightweight manycore processors with on-chip memory constraints.
Concurr. Comput. Pract. Exp., 2023
Parallelism in the Generation of Concepts Through the Formal Context Object Partitioning Using the In-Close 4 Algorithm.
Proceedings of the 25th International Conference on Enterprise Information Systems, 2023
2021
Inter-kernel communication facility of a distributed operating system for NoC-based lightweight manycores.
J. Parallel Distributed Comput., 2021
Co-Designing Clusters of Lightweight Manycores and Asymmetric Operating System Kernels.
IEEE Embed. Syst. Lett., 2021
An open computing language-based parallel Brute Force algorithm for formal concept analysis on heterogeneous architectures.
Concurr. Comput. Pract. Exp., 2021
2020
Reconfigurable FPGA-Based K-Means/K-Modes Architecture for Network Intrusion Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Hybrid Approach based on SARIMA and Artificial Neural Networks for Knowledge Discovery Applied to Crime Rates Prediction.
Proceedings of the 22nd International Conference on Enterprise Information Systems, 2020
Proceedings of the Enterprise Information Systems - 22nd International Conference, 2020
2019
A Fast Parallel K-Modes Algorithm for Clustering Nucleotide Sequences to Predict Translation Initiation Sites.
J. Comput. Biol., 2019
Concurr. Comput. Pract. Exp., 2019
On the Performance and Isolation of Asymmetric Microkernel Design for Lightweight Manycores.
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019
Teaching Parallel Programming to Freshmen in an Undergraduate Computer Science Program.
Proceedings of the IEEE Frontiers in Education Conference, 2019
2018
Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018
Design Space Exploration of Energy Efficient NoC-and Cache-Based Many-Core Architecture.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018
2017
IEICE Electron. Express, 2017
CAP Bench: a benchmark suite for performance and energy evaluation of low-power many-core processors.
Concurr. Comput. Pract. Exp., 2017
Design methodology for workload-aware loop scheduling strategies based on genetic algorithm and simulation.
Concurr. Comput. Pract. Exp., 2017
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017
Energy Consumption Improvement of Shared-Cache Multicore Clusters Based on Explicit Simultaneous Multithreading.
Proceedings of the 2017 International Symposium on Computer Architecture and High Performance Computing Workshops, 2017
Proceedings of the International Conference on Computational Science, 2017
2016
Parallelization of the next Closure algorithm for generating the minimum set of implication rules.
Artif. Intell. Res., 2016
Proceedings of the Euro-Par 2016: Parallel Processing Workshops, 2016
2015
On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms.
J. Parallel Distributed Comput., 2015
Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks.
J. Braz. Comput. Soc., 2015
2013
Method for teaching parallelism on heterogeneous many-core processors using research projects.
Proceedings of the IEEE Frontiers in Education Conference, 2013
2012
Parallel and distributed kmeans to identify the translation initiation site of proteins.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2012
Proceedings of the IEEE Frontiers in Education Conference, 2012
2011
Parallel Process. Lett., 2011
Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment.
Int. J. Reconfigurable Comput., 2011
2010
Proceedings of the 18th Euromicro Conference on Parallel, 2010
Proceedings of the 18th Euromicro Conference on Parallel, 2010
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
A Distributed Algorithm for Formal Concepts Processing based on Search Subspaces.
Proceedings of the ICEIS 2010 - Proceedings of the 12th International Conference on Enterprise Information Systems, Volume 1, DISI, Funchal, Madeira, Portugal, June 8, 2010
2009
Programmable multi-cluster noc architecture to support collective communication patterns.
PhD thesis, 2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
2008
Proceedings of the 11th IEEE International Conference on Computational Science and Engineering, 2008
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2003
Proceedings of the 2003 workshop on Computer architecture education, 2003
2001
Information Systems Planning: Contributions from Organizational Learning.
Proceedings of the ICEIS 2001, 2001