Henrik Hovsepyan

According to our database, Henrik Hovsepyan authored at least 4 papers between 2009 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Assesment of CPI Stress Impact on IC Reliability and Performance in 2.5D/3D Packages.

Armen Kteyan, Henrik Hovsepyan, Jun-Ho Choy, Valeriy Sukharev

Proceedings of the IEEE International Reliability Physics Symposium, 2019

2015

Post placement leakage reduction with stress-enhanced filler cells.

Jun-Ho Choy, Valeriy Sukharev, Armen Kteyan, Henrik Hovsepyan, Ramnath Venkatraman, Ruggero Castagnetti

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2012

Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance.

Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy, Henrik Hovsepyan, Ara Markosian, Ehrenfried Zschech, Rene Huebner

J. Electron. Test., 2012

2009

Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation.

Valeriy Sukharev, Ara Markosian, Armen Kteyan, Levon Manukyan, Nikolay Khachatryan, Jun-Ho Choy, Hasmik Lazaryan, Henrik Hovsepyan, Seiji Onoue, Takuo Kikuchi, Tetsuya Kamigaki

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009