Helmut E. Graeb

Proceedings of the 20th International Conference on Synthesis, 2024

2023

Learning from the Implicit Functional Hierarchy in an Analog Netlist.

[BibT_eX]

[DOI]

Markus Leibl

Proceedings of the 2023 International Symposium on Physical Design, 2023

2022

FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2022

A Hierarchical Performance Equation Library for Basic Op-Amp Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A functional block decomposition method for automatic op-amp design.

[BibT_eX]

[DOI]

Integr., 2022

Analog Synthesis - The Deterministic Way.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2021

COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing.

[BibT_eX]

[DOI]

Integr., 2021

Structure Synthesis of Op-Amps by Functional Block Composition.

[BibT_eX]

[DOI]

CoRR, 2021

An Efficient Programming Framework for Memristor-based Neuromorphic Computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Library-free Structure Recognition for Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Synthesis of DDRO Timing Monitors by Delay-Tracking and Static Timing Analysis.

[BibT_eX]

[DOI]

Jahnavi Kasturi Rangan

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

PASTEL: Parasitic Matching-Driven Placement and Routing of Capacitor Arrays With Generalized Ratios in Charge-Redistribution SAR-ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Verification and revision of the power-down mode for hierarchical analog circuits.

[BibT_eX]

[DOI]

Integr., 2020

Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies.

[BibT_eX]

[DOI]

Integr., 2020

A Hierarchical Performance Equation Library for Op-Amp Design.

[BibT_eX]

[DOI]

CoRR, 2020

Modeling and Optimization of a Microprobe Detector for Area and Yield Improvement.

[BibT_eX]

[DOI]

Alessandro Girardi

Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Recovery of 2D and 3D Layout Information through an Advanced Image Stitching Algorithm using Scanning Electron Microscope Images.

[BibT_eX]

[DOI]

Aayush Singla

Bernhard Lippmann

Proceedings of the 25th International Conference on Pattern Recognition, 2020

Hierarchical Analog Power-Down Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Structural Synthesis of Operational Amplifiers Based on Functional Block Modeling.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Synergetic Algorithm for Power-Down Synthesis.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2020

2019

MEMS-IC Robustness Optimization Considering Electrical and Mechanical Design and Process Parameters.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Derivative free methodologies for circuit worst case analysis.

[BibT_eX]

[DOI]

Optim. Lett., 2019

A 30 ns 16 Mb 2 b/cell Embedded Flash with Ramped Gate Time-Domain Sensing Scheme for Automotive Application.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

Power-Down Mode Verification for Hierarchical Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Synthesis, 2019

Verification of Physical Chip Layouts Using GDSII Design Data.

[BibT_eX]

[DOI]

Aayush Singla

Bernhard Lippmann

Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

Inversion-Coefficient-Aware Yield Optimization of Analog Circuits.

[BibT_eX]

[DOI]

Florin Burcea

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Constraint-Programmed Initial Sizing of Analog Operational Amplifiers.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Cross-Layer Interactions in CPS for Performance and Certification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Integrated flow for reverse engineering of nanoscale technologies.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

Bringing Analog Design Tools to Security: Modeling and Optimization of a Low Area Probing Detector.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Synthesis, 2018

Reverse Engineering of Cryptographic Cores by Structural Interpretation Through Graph Analysis.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Design-dependent Monitors Based on Delay Sensitivity Tracking.

[BibT_eX]

[DOI]

Jahnavi Kasturi Rangan

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

MEMS-IC Optimization Considering Design Parameters and Manufacturing Variation from both Mechanical and Electrical Side.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

On enabling diagnosis for 1-Pin Test fails in an industrial flow.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Analog Power-Down Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Realistic worst-case parameter sets for MEMS technologies.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Synthesis, 2017

A new robustness optimization methodology for MEMS-IC systems.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Synthesis, 2017

High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity.

[BibT_eX]

[DOI]

Florin Burcea

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A step-accurate model for the trapping and release of charge carriers suitable for the transient simulation of analog circuits.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

Efficient Evaluation of Physical Unclonable Functions Using Entropy Measures.

[BibT_eX]

[DOI]

Matthias Hiller

J. Circuits Syst. Comput., 2016

Power-down synthesis for analog circuits including switch sizing.

[BibT_eX]

[DOI]

Gaurav Shrivastava

Proceedings of the 13th International Conference on Synthesis, 2016

Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis.

[BibT_eX]

[DOI]

Florin Burcea

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

A fast analytical approach for static power-down mode analysis.

[BibT_eX]

[DOI]

Pantelis-Rafail Vlachas

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A pre-search assisted ILP approach to analog integrated circuit routing.

[BibT_eX]

[DOI]

Chia-Yu Wu

Jiang Hu

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Power-Down Circuit Synthesis for Analog/Mixed-Signal.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Detection of asymmetric aging-critical voltage conditions in analog power-down mode.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Advanced performance metrics for Physical Unclonable Functions.

[BibT_eX]

[DOI]

Akshara Ranjit Punnakkal

Matthias Hiller

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013

Evaluating analog circuit performance in light of MOSFET aging at different time scales.

[BibT_eX]

[DOI]

Proceedings of 2013 International Conference on IC Design & Technology, 2013

Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies.

[BibT_eX]

[DOI]

Veit Kleeberger

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

MARS: Matching-Driven Analog Sizing.

[BibT_eX]

[DOI]

Michael Eick

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

Tolerance Design of Analog Circuits using a Branch-and-Bound Based Approach.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2012

ITRS 2011 Analog EDA Challenges and Approaches.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Constraint-Based Layout-Driven Sizing of Analog Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

Reliability analysis of analog circuits by lifetime yield prediction using worst-case distance degradation rate.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Automatic generation of hierarchical placement rules for analog integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

Sizing analog circuits using an SQP and Branch and Bound based approach.

[BibT_eX]

[DOI]

Daniel Mueller-Gritschneder

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Computation of yield-optimized Pareto fronts for analog integrated circuit specifications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction.

[BibT_eX]

[DOI]

Daniel Mueller-Gritschneder

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems.

[BibT_eX]

[DOI]

SIAM J. Optim., 2009

Pareto optimization of analog circuits considering variability.

[BibT_eX]

[DOI]

Daniel Mueller-Gritschneder

Int. J. Circuit Theory Appl., 2009

Degradation-aware analog design flow for lifetime yield analysis and optimization.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

A free-shape router for analog and RF applications.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Analog layout synthesis - Recent advances in topological approaches.

[BibT_eX]

[DOI]

Francisco V. Fernández

Mark Po-Hung Lin

Martin Strasser

Proceedings of the Design, Automation and Test in Europe, 2009

Formal approaches to analog circuit verification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis.

[BibT_eX]

[DOI]

Tobias Massier

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Sizing Rules for Bipolar Analog Circuit Design.

[BibT_eX]

[DOI]

Tobias Massier

Proceedings of the Design, Automation and Test in Europe, 2008

From Transistor to PLL - Analogue Design and EDA Methods.

[BibT_eX]

[DOI]

David M. Binkley

Georges G. E. Gielen

Jaijeet S. Roychowdhury

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination.

[BibT_eX]

[DOI]

Guido Stehr

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Pareto-Front Computation and Automatic Sizing of CPPLLs.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming.

[BibT_eX]

[DOI]

Daniel Mueller

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Fast evaluation of analog circuit structures by polytopal approximations.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A CPPLL hierarchical optimization methodology considering jitter, power and locking time.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen.

[BibT_eX]

[DOI]

Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

Deterministic approaches to analog performance space exploration (PSE).

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing.

[BibT_eX]

[DOI]

Guido Stehr

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Performance trade-off analysis of analog circuits by normal-boundary intersection.

[BibT_eX]

[DOI]

Guido Stehr

Proceedings of the 40th Design Automation Conference, 2003

2002

Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits.

[BibT_eX]

[DOI]

Michael Pronath

Proceedings of the 2002 Design, 2002

2001

The Sizing Rules Method for Analog Integrated Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

A fast method for identifying matching-relevant transistor pairs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000

A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits.

[BibT_eX]

[DOI]

Michael Pronath

Volker Gloeckel

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

WiCkeD: analog circuit synthesis incorporating mismatch.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999

Analog testing by characteristic observation inference.

[BibT_eX]

[DOI]

Walter M. Lindermeir

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Simulationsbasierter Testentwurf für gemischt analog-digitale Systeme.

[BibT_eX]

[DOI]

Informationstechnik Tech. Inform., 1999

Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

Fast calculation of analog circuits' feasibility regions by low level functional measures.

[BibT_eX]

[DOI]

Stephan Zizala

Josef Eckmüller

Helmut Gräb

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults.

[BibT_eX]

[DOI]

Walter M. Lindermeir

Thomas J. Vogels

Proceedings of the 1998 Design, 1998

Hierarchical Characterization of Analog Integrated CMOS Circuits.

[BibT_eX]

[DOI]

Josef Eckmüller

Martin Groepl

Proceedings of the 1998 Design, 1998

1995

Design based analog testing by Characteristic Observation Inference.

[BibT_eX]

[DOI]

Walter M. Lindermeir

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Circuit analysis and optimization driven by worst-case distances.

[BibT_eX]

[DOI]

Claudia U. Wieser

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Fast transient power and noise estimation for VLSI circuits.

[BibT_eX]

[DOI]

Wolfgang T. Eisenmann

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Schaltkreisoptimierung mit Worst-Case-Abständen als Zielgrössen.

[BibT_eX]

[DOI]

Helmut Gräb

PhD thesis, 1993

Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances.

[BibT_eX]

[DOI]

Claudia U. Wieser

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Circuit yield optimization by analyzing performance statistics.

[BibT_eX]

[DOI]

Reiner E. Lederle

Microprocess. Microprogramming, 1992

Design verification considering manufacturing tolerances by using worst-caste distances.

[BibT_eX]

[DOI]

Claudia U. Wieser

Proceedings of the conference on European design automation, 1992

1991

Circuit Optimization Driven by Worst-Case Distances.

[BibT_eX]

[DOI]