Helia Naeimi

Suriyaprakash Natarajan

Arijit Raychowdhury

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Side Channel Attacks on STTRAM and Low-Overhead Countermeasures.

[BibT_eX]

[DOI]

Nitin Rathi

Swaroop Ghosh

CoRR, 2016

Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM.

[BibT_eX]

[DOI]

CoRR, 2016

Profile-Driven Automated Mixed Precision.

[BibT_eX]

[DOI]

CoRR, 2016

Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches.

[BibT_eX]

[DOI]

Mehdi Baradaran Tahoori

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Side channel attacks on STTRAM and low-overhead countermeasures.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Data privacy in non-volatile cache: Challenges, attack models and solutions.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays.

[BibT_eX]

[DOI]

Ashwin Chintaluri

Abhinav Parihar

Suriyaprakash Natarajan

Arijit Raychowdhury

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy.

[BibT_eX]

[DOI]

Proceedings of the International Conference for High Performance Computing, 2014

GangES: Gang error simulation for hardware resiliency evaluation.

[BibT_eX]

[DOI]

Radha Venkatagiri

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013

Relyzer: Application Resiliency Analyzer for Transient Faults.

[BibT_eX]

[DOI]

Pradeep Ramachandran

IEEE Micro, 2013

Recycled Error Bits: Energy-Efficient Architectural Support for Higher Precision Floating Point.

[BibT_eX]

[DOI]

CoRR, 2013

Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivity.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

2012

Low-cost program-level detectors for reducing silent data corruptions.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks, 2012

Relyzer: exploiting application-level fault equivalence to analyze application resiliency to transient faults.

[BibT_eX]

[DOI]

Pradeep Ramachandran

Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2011

A confidence-driven model for error-resilient computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

QED: Quick Error Detection tests for effective post-silicon validation.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Design techniques for cross-layer resilience.

[BibT_eX]

[DOI]

Nicholas P. Carter

Donald S. Gardner

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Fault Secure Encoder and Decoder for NanoMemory Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

2008

Reliable Integration of Terascale Systems with Nanoscale Devices.

[BibT_eX]

[DOI]

PhD thesis, 2008

2007

Fault tolerant nano-memory with fault secure encoder and decoder.

[BibT_eX]

[DOI]

Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Fault Secure Encoder and Decoder for Memory Applications.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2005

Seven Strategies for Tolerating Highly Defective Fabrication.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2005

2004

A greedy algorithm for tolerating defective crosspoints in nanoPLA design.

[BibT_eX]

[DOI]