Heinz Riener
Orcid: 0000-0003-1527-7160
According to our database1,
Heinz Riener
authored at least 54 papers
between 2011 and 2025.
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Bibliography
2025
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2025
2024
Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications.
CoRR, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits.
CoRR, 2021
Optimizing Adiabatic Quantum-Flux-Parametron (AQFP) Circuits using an Exact Database.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks.
IACR Cryptol. ePrint Arch., 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Formal Methods Syst. Des., 2019
Proceedings of the Reversible Computation - 11th International Conference, 2019
Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019
Proceedings of the 2019 Forum for Specification and Design Languages, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
2017
Int. J. Softw. Tools Technol. Transf., 2017
Counterexample-Guided EF Synthesis of Boolean Functions.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017
CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
Designing reliable cyber-physical systems overview associated to the special session at FDL'16.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
2015
Proceedings of the Proceedings 12th International Workshop on Formal Engineering approaches to Software Components and Architectures, 2015
Execution Tracing of C Code for Formal Analysis (Extended Abstract).
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
2014
A Logic for Cardinality Constraints (Extended Abstract).
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014
Proceedings of the 2014 Forum on Specification and Design Languages, 2014
2013
Yet a Better Error Explanation Algorithm (Extended Abstract).
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation.
Proceedings of the Model Checking Software - 19th International Workshop, 2012
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012
2011
Proceedings of the Fourth IEEE International Conference on Software Testing, 2011