Heinz Hoenigschmid

According to our database, Heinz Hoenigschmid authored at least 10 papers between 1997 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.

Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein

IEEE J. Solid State Circuits, 2010

2009

75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.

Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control.

Stefan Dietrich, Michael Angerbauer, Milena Ivanov, Dietmar Gogl, Heinz Hoenigschmid, Michael Kund, Corvin Liaw, Michael Markert, Ralf Symanczyk, Laith Altimime, Serge Bournat, Gerhard Müller

IEEE J. Solid State Circuits, 2007

2006

Signal-Margin-Screening for Multi-Mb MRAM.

Heinz Hoenigschmid, P. Beer, Alexander Bette, R. Dittrich, R. Gardic, Dietmar Gogl, Stefan Lammers, J. Schmid, Laith Altimime, Serge Bournat, Gerhard Müller

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A 16-Mb MRAM featuring bootstrapped write drivers.

Dietmar Gogl, Christian Arndt, John C. Barwin, Alexander Bette, John K. DeBrosse, Earl T. Gow, Heinz Hoenigschmid, Stefan Lammers, Mark C. Lamorey, Yu Lu, Tom Maffitt, Kim Maloney, Werner Obermaier, Andre Sturm, Hans Viehmann, Dennis R. Willmott, Mark A. Wood, William J. Gallagher, Gerhard Mueller, Arkalgud R. Sitaram

IEEE J. Solid State Circuits, 2005

2004

A high-speed 128-kb MRAM core for future universal memory applications.

John K. DeBrosse, Dietmar Gogl, Alexander Bette, Heinz Hoenigschmid, Raphael Robertazzi, Christian Arndt, Daniel Braun, D. Casarotto, Robert Havreluk, Stefan Lammers, Werner Obermaier, William R. Reohr, Hans Viehmann, William J. Gallagher, Gerhard Müller

IEEE J. Solid State Circuits, 2004

2000

A 7F² cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs.

Heinz Hoenigschmid, Alexander Frey, John K. DeBrosse, Toshiaki Kirihata, Gerhard Mueller, Daniel W. Storaska, Gabriel Daniel, Gerd Frankowsky, Kevin P. Guay, David R. Hanson, Louis Lu-Chen Hsu, Brian Ji, Dmitry G. Netis, Steve Panaroni, Carl Radens, Armin M. Reith, Hartmud Terletzki, Oliver Weinfurtner, Johann Alsmeier, Werner Weber, Matthew R. Wordeman

IEEE J. Solid State Circuits, 2000

A robust 8F² ferroelectric RAM cell with depletion device (DeFeRAM).

Georg Braun, Heinz Hoenigschmid, Tobias Schlager, Werner Weber

IEEE J. Solid State Circuits, 2000

1999

A 390-mm², 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture.

Toshiaki Kirihata, Gerhard Mueller, Brian Ji, Gerd Frankowsky, John M. Ross, Hartmud Terletzki, Dmitry G. Netis, Oliver Weinfurtner, David R. Hanson, Gabriel Daniel, Louis Lu-Chen Hsu, Daniel W. Storaska, Armin M. Reith, Marco A. Hug, Kevin P. Guay, Manfred Selz, Peter Poechmueller, Heinz Hoenigschmid, Matthew R. Wordeman

IEEE J. Solid State Circuits, 1999

1997

Optimization of advanced MOS technologies for narrow distribution of circuit performance.

Heinz Hoenigschmid, Mitiko Miura-Manausch, Odin Prigge, Alexander Rahm, Dominique Savignac

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997