Heinrich Theodor Vierhaus

Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik, Energie und Umwelt, INFORMATIK 2015, Cottbus, Germany, September 28, 2015

Test eingebetteter Prozessoren im Zielsystem mit hoher diagnostischer Auflösung.

[BibT_eX]

[DOI]

Christian Gleichner

Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik, Energie und Umwelt, INFORMATIK 2015, Cottbus, Germany, September 28, 2015

Detection and Correction of Logic Errors Using Extra Time Slots.

[BibT_eX]

[DOI]

Davide Dicorato

Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik, Energie und Umwelt, INFORMATIK 2015, Cottbus, Germany, September 28, 2015

Compiler-Centred Microprocessor Design (CoMet) - From C-Code to a VHDL Model of an ASIP.

[BibT_eX]

[DOI]

Roberto Urban

Enrico Altmann

Horst Seelig

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Combining Correction of Delay Faults and Transient Faults.

[BibT_eX]

[DOI]

Stefan Scharoba

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Redundancy evaluation process of processor components for permanent fault compensation.

[BibT_eX]

[DOI]

Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014

Vergleich der Beschreibung und Simulation einer Befehlssatzarchitektur in LISA und CoMet.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Timing for virtual TMR in logic circuits.

[BibT_eX]

[DOI]

Sebastian Müller

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Advanced technical education in the age of cyber physical systems.

[BibT_eX]

[DOI]

Jaan Raik

Raimund Ubar

Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

Systematic generation of diagnostic software-based self-test routines for processor components.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Reconfigurable high performance architectures: How much are they ready for safety-critical applications?

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Combining fault tolerance and self repair at minimum cost in power and hardware.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013

Towards a Graceful Degradable Multicore-System by Hierarchical Handling of Hard Errors.

[BibT_eX]

[DOI]

Sebastian Müller

Proceedings of the 21st Euromicro International Conference on Parallel, 2013

Ein konfigurierbarer Zwischencodesimulator zum compilerzentrierten Mikroprozessorentwurf.

[BibT_eX]

Roberto Urban

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Towards an automatic generation of diagnostic in-field SBST for processor components.

[BibT_eX]

[DOI]

Stephanie Roder

Proceedings of the 14th Latin American Test Workshop, 2013

Virtual TMR Schemes Combining Fault Tolerance and Self Repair.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

On performance estimation of a scalable VLIW soft-core in XILINX FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

On the feasibility of combining on-line-test and self repair for logic circuits.

[BibT_eX]

[DOI]

Piet Engelke

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

Activity Migration in M-of-N-Systems by Means of Load-Balancing.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Scan Based Tests via Standard Interfaces.

[BibT_eX]

[DOI]

Christian Gleichner

Piet Engelke

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores.

[BibT_eX]

[DOI]

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Combining on-line fault detection and logic self repair.

[BibT_eX]

[DOI]

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Hierarchical Self-repair in Heterogeneous Multi-core Systems by Means of a Software-based Reconfiguration.

[BibT_eX]

[DOI]

Sebastian Müller

Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011

On the Feasibility of Built-In Self Repair for Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Combining de-stressing and self repair for long-term dependable systems.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A software-based self-test and hardware reconfiguration solution for VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

A Concept for Logic Self Repair.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Reliability Estimation Process.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A scheme of logic self repair including local interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

Simulated fault injections and their acceleration in SystemC.

[BibT_eX]

[DOI]

André Sieber

Microprocess. Microsystems, 2008

A Scan Controller Concept for Low Power Scan Tests.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

Basic Architecture for Logic Self Repair.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Embedded Diagnostic Logic Test Exploiting Regularity.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

A Configurable Modular Test Processor and Scan Controller Architecture.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Timing- / Power-Optimization for Digital Logic Based on Standard Cells.

[BibT_eX]

[DOI]

Helmut Rossmann

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Fault Injection Techniques and their Accelerated Simulation in SystemC.

[BibT_eX]

[DOI]

André Sieber

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Flip-Flops and Scan-Path Elements for Nanoelectronics.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Timing-/Power-getriebener Layout-Entwurf für Zellen-basierte Digitalschaltungen.

[BibT_eX]

Axel Vick

Helmut Rossmann

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

Built-in Self Repair by Reconfiguration of FPGAs.

[BibT_eX]

[DOI]

S. Habermann

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Embedded Scan Test with Diagnostic Features for Self-Testing SoCs.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

A Mixed Language Fault Simulation of VHDL and SystemC.

[BibT_eX]

[DOI]

Lars Breitenfeld

André Sieber

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes.

[BibT_eX]

[DOI]

U. Gätzschmann

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Embedded Self Repair by Transistor and Gate Level Reconfiguration.

[BibT_eX]

[DOI]

Torsten Coym

Wolfgang Vermeiren

Bernd Straube

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Hardware/Software Based Hierarchical Self Test for SoCs.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Evaluating coverage of error detection logic for soft errors using formal methods.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Logic Self Repair.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2006, 2006

2005

Synchronization Fault Cryptanalysis for Breaking A5/1.

[BibT_eX]

[DOI]

Marcin Gomulkiewicz

Miroslaw Kutylowski

Pawel Wlaz

Proceedings of the Experimental and Efficient Algorithms, 4th InternationalWorkshop, 2005

A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Power-/Timing - Optimierung für Zellen-basierte Digitalschaltungen in Submikron-Technologien.

[BibT_eX]

[DOI]

Helmut Rossmann

Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

2004

FIT - A Parallel Hierarchical Fault Simulation Environment.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

A Hierarchical Self Test Scheme for SoCs.

[BibT_eX]

[DOI]

Claudia Kretzschmar

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

2003

On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check.

[BibT_eX]

[DOI]

Karsten Walther

J. Electron. Test., 2003

Control Signal Protection For High Performance Processors.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip.

[BibT_eX]

[DOI]

Marcus Grabow

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

2002

On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check.

[BibT_eX]

[DOI]

Karsten Walther

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

A Test Processor Concept for Systems-on-a-Chip.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

Online Check and Recovery Techniques for Dependable Embedded Processors.

[BibT_eX]

[DOI]

IEEE Micro, 2001

On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity.

[BibT_eX]

[DOI]

Karsten Walther

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A register-transfer-level fault simulator for permanent and transient faults in embedded processors.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

A new method for on-line state machine observation for embedded microprocessors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

1999

SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information.

[BibT_eX]

[DOI]

Massimo Violante

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

An efficient on-line-test and back-up scheme for embedded processors.

[BibT_eX]

[DOI]

F. Pompsch

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Generating reliable embedded processors.

[BibT_eX]

[DOI]

IEEE Micro, 1998

1997

Partitioning and analysis of static digital CMOS circuits.

[BibT_eX]

[DOI]

Raul Camposano

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

A Parallel Approach Solving the Test Generation Problem for Synchronous Sequential Circuits.

[BibT_eX]

H.-Ch. Dahmen

Proceedings of the Parallel Computing: Fundamentals, 1997

An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation.

[BibT_eX]

[DOI]

H.-Ch. Dahmen

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1996

Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Automatic Test Pattern Generation with Optimal Load Balancing.

[BibT_eX]

[DOI]

H.-Ch. Dahmen

Proceedings of the Parallel Virtual Machine, 1996

A Design Exploration Environment.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

Improving topological ATPG with symbolic techniques.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

FOGBUSTER: an efficient algorithm for sequential test generation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

Gate delay fault test generation for non-scan circuits.

[BibT_eX]

[DOI]

G. Van Brakel

Hans G. Kerkhoff

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Testability Analysis for Test Generation in Synchronous Sequential Circuits.

[BibT_eX]

[DOI]

R. Wolber

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation.

[BibT_eX]

[DOI]

M. Kley

A. Wiederhold

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Local microcode generation in system design.

[BibT_eX]

Michel Langevin

Eduard Cerny

Jörg Wilberg

Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

1993

Fault behavior and testability of asynchronous CMOS circuits.

[BibT_eX]

[DOI]

Wolfgang Meyer

Raul Camposano

Microprocess. Microprogramming, 1993

CMOS Bridges and Resistive Transistor Faults: I<sub>DDQ</sub> versus Delay Effects.

[BibT_eX]

[DOI]

Wolfgang Meyer

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992

CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents.

[BibT_eX]

[DOI]

Wolfgang Meyer

Microprocess. Microprogramming, 1992

Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Library Mapping of CMOS-Switch-Level-Circuits by Extraction of Isomorphic Subgraphs.

[BibT_eX]

[DOI]

Ursula Westerholz

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Efficient partitioning and analysis of digital CMOS-circuits.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

MILEF: an efficient approach to mixed level automatic test pattern generation.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

1991

Mixed level test generation for high fault coverage.

[BibT_eX]

[DOI]

H. Hinsen

M. Hofebauer

Microprocessing and Microprogramming, 1991

1990

CMOS layout generation for improved testability.

[BibT_eX]

[DOI]

Olaf Stern

Microprocessing and Microprogramming, 1990

1989

Testability of non-trivial CMOS faults under realistic conditions.

[BibT_eX]

[DOI]

Microprocessing and Microprogramming, 1989

1988

CMOS fault modeling, test generation and design for testability.

[BibT_eX]

[DOI]