Heiko Hinkelmann

Orcid: 0000-0003-0982-034X

According to our database1, Heiko Hinkelmann authored at least 28 papers between 2004 and 2023.

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Bibliography

2023
An Efficient Feature-based Method for People Counting.
Proceedings of the 38th ACM/SIGAPP Symposium on Applied Computing, 2023

2012
Entwurf und Energieeffizienzanalyse von dynamisch rekonfigurierbaren Architekturen für drahtlose Sensorknoten.
PhD thesis, 2012

2010
Dynamically Reconfigurable Systems for Wireless Sensor Networks.
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009
On the design of reconfigurable multipliers for integer and Galois field multiplication.
Microprocess. Microsystems, 2009

Towards a unique FPGA-based identification circuit using process variations.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable Processor.
Proceedings of the Distributed Embedded Systems: Design, 2008

An area-efficient FPGA realisation of a codebook-based image compression method.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

A scalable reconfiguration mechanism for fast dynamic reconfiguration.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Application-specific reconfigurable processors.
Proceedings of the FPL 2008, 2008


2007
Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme).
it Inf. Technol., 2007

A Customizable LEON2-Based VLIW Processor.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A Power Estimation Model for an FPGA-based Softcore Processor.
Proceedings of the FPL 2007, 2007

2006
Exploring Functional Unit Parallelism in Reconfigurable Computing Platforms.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A Concept for a Profile-based Dynamic Reconfiguration Mechanism.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Multitasking Support for Dynamically Reconfig Urable Systems.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A metric for the energy-efficiency of dynamically reconfigurable systems.
Proceedings of the ARCS 2006, 2006

Design Concepts for a Dynamically ReconfigurableWireless Sensor Node.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten.
Proceedings of the 18th International Conference on Architecture of Computing Systems, 2005

2004
A switch architecture and signal synchronization for GALS system-on-chips.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

An Asynchronous Switch Implmentation for Systems-on-a-Chip.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004


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