Héctor Posadas

Orcid: 0000-0002-1427-7524

According to our database1, Héctor Posadas authored at least 50 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
CNN-LSTM Implementation Methodology on SoC FPGA for Human Action Recognition Based on Video.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

2023
Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards.
IEEE Embed. Syst. Lett., September, 2023

UML-Based Design Flow for Systems with Neural Networks.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

Automatic code generation from UML for data memory optimization in microcontrollers.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2021
Modeling and Performance Estimation of Robotic Systems using ROS: Application to drone-based Services.
Proceedings of the 24th Forum on specification & Design Languages, 2021

Multilevel host-compiled simulation framework for ROS-based UAV services using ArduCopter.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020
Mega-modeling of complex, distributed, heterogeneous CPS systems.
Microprocess. Microsystems, 2020

Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Data flow analysis from UML/MARTE models based on binary traces.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019
Accelerating Host-Compiled Simulation by Modifying IR Code: Industrial application in the spatial domain.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2017
High-Level Design of Wireless Sensor Networks for Performance Optimization Under Security Hazards.
ACM Trans. Sens. Networks, 2017

Synthesis of simulation and implementation code for OpenMAX multimedia heterogeneous systems from UML/MARTE models.
Multim. Tools Appl., 2017

Static Write Buffer Cache Modeling to Increase Host-Compiled Simulation Accuracy.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Using Professional Resources for Teaching Embedded SW Development.
Rev. Iberoam. de Tecnol. del Aprendiz., 2016

2015
Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics.
J. Syst. Archit., 2015

2014
Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation.
Microelectron. J., 2014

Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project.
Microprocess. Microsystems, 2014

The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems.
J. Syst. Archit., 2014

A framework for design space exploration and performance analysis of networked embedded systems.
Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2014

Automatic Synthesis over Multiple APIs from Uml/Marte Models for Easy Platform Mapping and Reuse.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013
EU FP7-288307 Pharaon Project: Parallel and Heterogeneous Architecture for Real-Time Applications.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Early Performance Evaluation of Multi-OS Embedded Platforms Using Native Simulation.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Automatic synthesis from UML/MARTE models using channel semantics.
Proceedings of the 5th International Workshop on Model Based Architecting and Construction of Embedded Systems, 2012

Model-Driven Methodology for the Development of Multi-level Executable Environments.
Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

A model-driven methodology for the development of SystemC executable environments.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

The COMPLEX Eclipse framework for UML/MARTE specification and design space exploration of embedded systems.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design.
J. Low Power Electron., 2011

Early, time-approximate modeling of multi-OS. linux platforms in a systemC co-simulation environment.
Comput. Syst. Sci. Eng., 2011

Fast data-cache modeling for native co-simulation.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011


M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

High-level modeling and exploration of a powerline communication network based on System-on-Chip.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

2010
Generating heterogeneous executable specifications in SystemC from UML/MARTE models.
Innov. Syst. Softw. Eng., 2010

L2 Cache Modeling based on address modification for Native Co-Simulation in SystemC.
Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010


Early Modeling of Linux-Based RTOS Platforms in a SystemC Time-Approximate Co-simulation Environment.
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2010

Formal Modeling for UML/MARTE Concurrency Resources.
Proceedings of the 15th IEEE International Conference on Engineering of Complex Computer Systems, 2010

Fast instruction cache modeling for approximate timed HW/SW co-simulation.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Modeling Separate Memory Spaces in Native Co-simulation with SystemC for Design Space Exploration.
Proceedings of the ARCS '10, 2010

2009
Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulation.
Proceedings of the Analysis, 2009

2007
Protocol Bus Modeling using inheritance with TLM2.0.
Proceedings of the Forum on specification and Design Languages, 2007

2006
POSIX modeling in SystemC.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model.
Des. Autom. Embed. Syst., 2005

2004
Single Source Design Environment for Embedded Systems Based on SystemC.
Des. Autom. Embed. Syst., 2004

System-Level Performance Analysis in SystemC.
Proceedings of the 2004 Design, 2004

Platform Based on Open-Source Cores for Industrial Applications.
Proceedings of the 2004 Design, 2004

2003
Systemic Embedded Software Generation from SystemC.
Proceedings of the 2003 Design, 2003

Systematic Embedded Software Generation from Systemc.
Proceedings of the Embedded Software for SoC, 2003


  Loading...