Héctor Pettenghi

According to our database, Héctor Pettenghi authored at least 27 papers between 2004 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Comprehensive Approach and Analysis of Reverse Converters for a Class of Moduli Sets.

Gabriel Fernandes, Augusto Vassoler, Eduardo Bezerra, Leonel Sousa, Héctor Pettenghi

Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023

RNS processor using moduli sets of the form 2^<i>n</i>±1.

Vanessa Prediger, Fábio Bairros, Laio Oriel Seman, Eduardo Augusto Bezerra, Héctor Pettenghi

Int. J. Circuit Theory Appl., July, 2023

2020

Towards the Integration of Reverse Converters into the RNS Channels.

Leonel Sousa, Rogerio Paludo, Paulo Martins, Héctor Pettenghi

IEEE Trans. Computers, 2020

2019

Introducing Asymmetry in a CMOS Latch to Obtain Inherent Power-On-Reset Behavior.

Fabián Leonardo Cabrera, Fernando Rangel de Sousa, Héctor Pettenghi

Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2018

Efficient RNS Reverse Converters for Moduli Sets with Dynamic Ranges Up to \((10n+1)\) -bit.

Héctor Pettenghi, Rogerio Paludo, Roberto de Matos, Pavel Alekseevich Lyakhov

Circuits Syst. Signal Process., 2018

2017

Efficient implementation of modular multiplication by constants applied to RNS reverse converters.

Roberto de Matos, Rogerio Paludo, Nikolay I. Chervyakov, Pavel Alekseevich Lyakhov, Héctor Pettenghi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Method for designing two levels RNS reverse converters for large dynamic ranges.

Héctor Pettenghi, Ricardo Chaves, Roberto de Matos, Leonel Sousa

Integr., 2016

RNS reverse converters for moduli sets with dynamic ranges of 9n-bit.

Héctor Pettenghi, Roberto de Matos, Amir Sabbagh Molahosseini

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015

RNS reverse converters based on the new Chinese Remainder Theorem I.

Héctor Pettenghi, Leonel Sousa

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

Efficient Method for Designing Modulo {2ⁿ ± k} Multipliers.

Héctor Pettenghi, Sorin Cotofana, Leonel Sousa

J. Circuits Syst. Comput., 2014

Method for Designing Efficient Mixed Radix Multipliers.

Héctor Pettenghi, Frederico Pratas, Leonel Sousa

Circuits Syst. Signal Process., 2014

Method for designing multi-channel RNS architectures to prevent power analysis SCA.

Héctor Pettenghi, Jude Angelo Ambrose, Ricardo Chaves, Leonel Sousa

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Method to Design General RNS Reverse Converters for Extended Moduli Sets.

Héctor Pettenghi, Ricardo Chaves, Leonel Sousa

IEEE Trans. Circuits Syst. II Express Briefs, 2013

RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to (8n+1)-bit.

Héctor Pettenghi, Ricardo Chaves, Leonel Sousa

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks.

Jude Angelo Ambrose, Héctor Pettenghi, Darshana Jayasinghe, Leonel Sousa

IET Circuits Devices Syst., 2013

DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks.

Jude Angelo Ambrose, Héctor Pettenghi, Leonel Sousa

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

RNS Arithmetic Units for Modulo {2^n+-k}.

Pedro Miguens Matutino, Héctor Pettenghi, Ricardo Chaves, Leonel Sousa

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion.

Héctor Pettenghi, Leonel Sousa, Jude Angelo Ambrose

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2010

An improved RNS generator 2ⁿ +/- k based on threshold logic.

Héctor Pettenghi, Ricardo Chaves, Leonel Sousa, Maria J. Avedillo

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

2009

Operation Limits for RTD-Based MOBILE Circuits.

José M. Quintana, Maria J. Avedillo, Juan Núñez, Héctor Pettenghi

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008

Using multi-threshold threshold gates in RTD-based logic design: A case study.

Héctor Pettenghi, Maria J. Avedillo, José M. Quintana

Microelectron. J., 2008

A novel contribution to the RTD-based threshold logic family.

Héctor Pettenghi, Maria J. Avedillo, José M. Quintana

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Non Return Mobile Logic Family.

Héctor Pettenghi, Maria J. Avedillo, José M. Quintana

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors.

Maria J. Avedillo, José M. Quintana, Héctor Pettenghi Roldán

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Self-latching operation limits for MOBILE circuits.

José M. Quintana, Maria J. Avedillo, Héctor Pettenghi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Logic Models Supporting the Design of MOBILE-based RTD Circuits.

Maria J. Avedillo, José M. Quintana, Héctor Pettenghi

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

Programmable logic gate based on resonant tunnelling devices.

José M. Quintana, Maria J. Avedillo, Héctor Pettenghi

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004