Hayoung Lee

Orcid: 0000-0002-6868-0829

According to our database¹, Hayoung Lee authored at least 43 papers between 2013 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2024

An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator.

[BibT_eX]

[DOI]

Hayoung Lee

Jongho Park

Sungho Kang

IEEE Trans. Very Large Scale Integr. Syst., October, 2024

GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults.

[BibT_eX]

[DOI]

Seung Ho Shin

Hayoung Lee

Sungho Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

Leveraging Medical Knowledge Graphs and Large Language Models for Enhanced Mental Disorder Information Extraction.

[BibT_eX]

[DOI]

Chaelim Park

Hayoung Lee

OkRan Jeong

Future Internet, August, 2024

A New ISA for High-Speed and Area-Efficient ALPG.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

RA-Aware Fail Data Collection Architecture for Cost Reduction.

[BibT_eX]

[DOI]

Hayoung Lee

Sooryeong Lee

Sungho Kang

IEEE Trans. Very Large Scale Integr. Syst., June, 2024

A New Fail Address Memory Architecture for Cost-Effective ATE.

[BibT_eX]

[DOI]

Hayoung Lee

Sooryeong Lee

Sungho Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

HyperCLOVA X Technical Report.

[BibT_eX]

[DOI]

CoRR, 2024

An Efficient Scan Diagnosis for Intermittent Faults Using CNN With Multi-Channel Data.

[BibT_eX]

[DOI]

IEEE Access, 2024

APAPG: Address Pre-Processed ALPG for High-Speed Linear Test.

[BibT_eX]

[DOI]

Proceedings of the 21st International SoC Design Conference, 2024

Scan Architecture with Data Observation for Multiple Scan Cell Fault Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 21st International SoC Design Conference, 2024

2023

STRAIT: Self-Test and Self-Recovery for AI Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

TRUST: Through-Silicon via Repair Using Switch Matrix Topology.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

A Knowledge-Grounded Task-Oriented Dialogue System with Hierarchical Structure for Enhancing Knowledge Selection.

[BibT_eX]

[DOI]

Hayoung Lee

Okran Jeong

Sensors, January, 2023

Sentiment analysis and counselling for COVID-19 pandemic based on social media.

[BibT_eX]

[DOI]

Hayoung Lee

Ok-Ran Jeong

Int. J. Web Grid Serv., 2023

HPCClusterScape: Increasing Transparency and Efficiency of Shared High-Performance Computing Clusters for Large-scale AI Models.

[BibT_eX]

[DOI]

CoRR, 2023

GPU-Based Redundancy Analysis using Partitioning Method for Memory Repair.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

Redundancy Analysis Simplification Scheme for High-Speed Memory Repair.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

2022

ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Multibank Optimized Redundancy Analysis Using Efficient Fault Collection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An Improved Early Termination Methodology Using Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

FAME: Fault Address Memory Structure for Repair Time Reduction.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

PROG: Per-Row Output Generator for BOST.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

ZOS: Zero Overhead Scan for Systolic Array-based AI accelerator.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

2021

On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug.

[BibT_eX]

[DOI]

Hayoung Lee

Hyunggoy Oh

Sungho Kang

IEEE Access, 2021

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory.

[BibT_eX]

[DOI]

IEEE Access, 2021

Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory.

[BibT_eX]

[DOI]

Donghyun Han

Hayoung Lee

Sungho Kang

IEEE Access, 2021

Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

2020

GPU-Based Redundancy Analysis Using Concurrent Evaluation.

[BibT_eX]

[DOI]

Tae Hyun Kim

Hayoung Lee

Sungho Kang

IEEE Trans. Very Large Scale Integr. Syst., 2020

Fine-Grained Defect Diagnosis for CMOL FPGA Circuits.

[BibT_eX]

[DOI]

IEEE Access, 2020

Fail Memory Configuration Set for RA Estimation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

W-ERA: One-Time Memory Repair with Wafer-Level Early Repair Analysis for Cost Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2020

Memory-like Defect Diagnosis for CMOL FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2020

2019

Dynamic Built-In Redundancy Analysis for Memory Repair.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Redundancy Analysis based on Fault Distribution for Memory with Complex Spares.

[BibT_eX]

[DOI]

Proceedings of the 2019 International SoC Design Conference, 2019

2018

An Area-Efficient BIRA With 1-D Spare Segments.

[BibT_eX]

[DOI]

Donghyun Kim

Hayoung Lee

Sungho Kang

IEEE Trans. Very Large Scale Integr. Syst., 2018

Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2018

Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

3D Memory Formed of Unrepairable Memory Dice and Spare Layer.

[BibT_eX]

[DOI]

Proceedings of the TENCON 2018, 2018

2017

A new repair scheme for TSV-based 3D memory using base die repair cells.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

2016

Discussion of cost-effective redundancy architectures.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

2013

Punobot: Mobile Botnet Using Push Notification Service in Android.

[BibT_eX]

[DOI]

Proceedings of the Information Security Applications - 14th International Workshop, 2013

Hayoung Lee

Timeline

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