Hayato Yamaki

According to our database, Hayato Yamaki authored at least 16 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Analyzing the impact of CUDA versions on GPU applications.

Kohei Yoshida, Shinobu Miwa, Hayato Yamaki, Hiroki Honda

Parallel Comput., 2024

CNFET-OCL: Open-Source Cell Libraries for Advanced CNFET Technologies.

Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda

IEEE Access, 2024

Evaluating MPI Performance on SGX and Gramine.

Kota Shimojima, Shinobu Miwa, Hayato Yamaki, Hiroki Honda

Proceedings of the IEEE International Conference on Cluster Computing, 2024

Power-Efficiency Variation on A64FX Supercomputers and its Application to System Operation.

Tomoya Kusaba, Yusuke Awaki, Kohei Yoshida, Shinobu Miwa, Hayato Yamaki, Toshihiro Hanawa, Hiroki Honda

Proceedings of the IEEE International Conference on Cluster Computing, 2024

2023

CNFET7: An Open Source Cell Library for 7-nm CNFET Technology.

Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Analyzing Performance and Power-Efficiency Variations among NVIDIA GPUs.

Kohei Yoshida, Rio Sageyama, Shinobu Miwa, Hayato Yamaki, Hiroki Honda

Proceedings of the 51st International Conference on Parallel Processing, 2022

2021

Packet Forwarding Cache of Commodity Switches for Parallel Computers.

Shoichi Hirasawa, Hayato Yamaki, Michihiro Koibuchi

Proceedings of the IEEE International Conference on Cluster Computing, 2021

2020

Footprint-Based DIMM Hotplug.

Shinobu Miwa, Masaya Ishihara, Hayato Yamaki, Hiroki Honda, Martin Schulz

IEEE Trans. Computers, 2020

Effective cache replacement policy for packet processing cache.

Hayato Yamaki

Int. J. Commun. Syst., 2020

RPC: An Approach for Reducing Compulsory Misses in Packet Processing Cache.

Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda

IEICE Trans. Inf. Syst., 2020

Evaluating architecture-level optimization in packet processing caches.

Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda

Comput. Networks, 2020

2019

Functionally-Predefined Kernel: a Way to Reduce CNN Computation.

Yuta Inouchi, Hayato Yamaki, Shinobu Miwa, Tomoaki Tsumura

Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

Multi-Level Packet Processing Caches.

Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

2018

Data prediction for response flows in packet processing cache.

Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda

Proceedings of the 55th Annual Design Automation Conference, 2018

2016

Line Replacement Algorithm for L1-scale Packet Processing Cache.

Hayato Yamaki, Hiroaki Nishi

Proceedings of the Adjunct Proceedings of the 13th International Conference on Mobile and Ubiquitous Systems: Computing Networking and Services, 2016

Initial Study of Reconfigurable Neural Network Accelerators.

Momoka Ohba, Satoshi Shindo, Shinobu Miwa, Tomoaki Tsumura, Hayato Yamaki, Hiroki Honda

Proceedings of the Fourth International Symposium on Computing and Networking, 2016