Hayate Okuhara

According to our database, Hayate Okuhara authored at least 37 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing.

Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini

IEEE J. Solid State Circuits, January, 2024

SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks.

Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024

2023

A Scalable Body Bias Optimization Method Toward Low-Power CGRAs.

Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano

IEEE Micro, 2023

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing.

Francesco Conti, Gianna Paulin, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini

CoRR, 2023

A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing.

Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, Mathieu Louvat, Emmanuel Botte, Luca Benini

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes.

Karim Ali Ahmed, Hayate Okuhara, Massimo Alioto

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

Body Bias Control on a CGRA based on Convex Optimization.

Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022

2021

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS.

Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi

IEEE Trans. Very Large Scale Integr. Syst., 2021

A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL.

Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS.

Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi

CoRR, 2021

2020

Flexible Software-Defined Packet Processing Using Low-Area Hardware.

Hesam Zolfaghari, Davide Rossi, Walter Cerroni, Hayate Okuhara, Carla Raffaelli, Jari Nurmi

IEEE Access, 2020

An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes.

Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Palestri, Luca Benini

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

A Preliminary Evaluation of Building Block Computing Systems.

Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Mitaro Namiki

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration.

Hayate Okuhara, Ryosuke Kazami, Hideharu Amano

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process.

Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano

Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019

2018

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization.

Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano

IEEE Trans. Very Large Scale Integr. Syst., 2018

Body Bias Control for Renewable Energy Source with a High Inner Resistance.

Keita Azegami, Hayate Okuhara, Hideharu Amano

IEEE Trans. Multi Scale Comput. Syst., 2018

Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems.

Hayate Okuhara, Akram Ben Ahmed, Hideharu Amano

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach.

Carlos Cesar Cortes Torres, Hayate Okuhara, Nobuyuki Yamasaki, Hideharu Amano

IEICE Trans. Inf. Syst., 2018

Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures.

Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano

IEICE Trans. Inf. Syst., 2018

Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems.

Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping.

Takuya Kojima, Naoki Ando, Yusuke Matshushita, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

Design automation methodology of a critical path monitor for adaptive voltage controls.

Ryosuke Kazami, Hayate Okuhara, Hideharu Amano

Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

2017

Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET.

Hayate Okuhara, Yu Fujita, Kimiyoshi Usami, Hideharu Amano

IEEE Trans. Very Large Scale Integr. Syst., 2017

Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator.

Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano

IEICE Trans. Inf. Syst., 2017

Glitch-aware variable pipeline optimization for CGRAs.

Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA.

Nguyen Anh Vu Doan, Yusuke Matsushita, Naoki Ando, Hayate Okuhara, Hideharu Amano

Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Body bias optimization for variable pipelined CGRA.

Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Leveraging asymmetric body bias control for low power LSI design.

Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano

Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

2016

Variable pipeline structure for Coarse Grained Reconfigurable Array CMA.

Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Body bias grain size exploration for a coarse grained reconfigurable accelerator.

Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

MuCCRA4-BB: A fine-grained body biasing capable DRP.

Johannes Maximilian Kühn, Akram Ben Ahmed, Hayate Okuhara, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel

Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

2015

A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2.

Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET.

Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB.

Yu Fujita, Hayate Okuhara, Koichiro Masuyama, Hideharu Amano

Proceedings of the Third International Symposium on Computing and Networking, 2015

7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2.

Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control.

Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano

Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015