Hassan Nassar

Orcid: 0000-0003-1566-8997

According to our database1, Hassan Nassar authored at least 17 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2021
2022
2023
2024
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4
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Legend:

Book 
In proceedings 
Article 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
Meta-Scanner: Detecting Fault Attacks via Scanning FPGA Designs Metadata.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

Hacking the Fabric: Targeting Partial Reconfiguration for Fault Injection in FPGA Fabrics.
CoRR, 2024

An FPGA-Based RISC-V Instruction Set Extension and Memory Controller for Multi-Level Cell NVM.
Proceedings of the International Conference on Microelectronics, 2024

Client-Server Framework for FPGA Acceleration of Fan-Vercauteren-Based Homomorphic Encryption.
Proceedings of the International Conference on Microelectronics, 2024

LightFAt: Mitigating Control-Flow Explosion via Lightweight PMU-Based Control-Flow Attestation.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

HBMorphic: FHE Acceleration via HBM-Enabled Recursive Karatsuba Multiplier on FPGA.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

2023
Swift-CNN: Leveraging PCM Memory's Fast Write Mode to Accelerate CNNs.
IEEE Embed. Syst. Lett., December, 2023

Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-Based Accelerators.
IEEE Embed. Syst. Lett., December, 2023

ANV-PUF: Machine-Learning-Resilient NVM-Based Arbiter PUF.
ACM Trans. Embed. Comput. Syst., October, 2023

Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Supporting Dynamic Control-Flow Execution for Runtime Reconfigurable Processors.
Proceedings of the International Conference on Microelectronics, 2023

Late Breaking Results: Configurable Ring Oscillators as a Side-Channel Countermeasure.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
CaPUF: Cascaded PUF Structure for Machine Learning Resiliency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

TiVaPRoMi: Time-Varying Probabilistic Row-Hammer Mitigation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021


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