Hassan Daryanavard

Orcid: 0000-0002-6525-2562

According to our database1, Hassan Daryanavard authored at least 6 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A novel multiplier-less convolution core for YOLO CNN ASIC implementation.
J. Real Time Image Process., April, 2024

High-speed YOLOv4-tiny hardware accelerator for self-driving automotive.
J. Supercomput., March, 2024

2023
Scalable and custom-precision floating-point hardware convolution core for using in AI edge processors.
J. Real Time Image Process., October, 2023

Energy-efficient approximate full adders for error-tolerant applications.
Comput. Electr. Eng., September, 2023

A Low-Power Improved-Accuracy Approximate Error-Report-Propagate Adder for DSP Applications.
Circuits Syst. Signal Process., June, 2023

2008
On the Design of Architectural Pattern to Develop Dynamically Reconfigurable Autonomic Component.
Proceedings of the NCM 2008, The Fourth International Conference on Networked Computing and Advanced Information Management, Gyeongju, Korea, September 2-4, 2008, 2008


  Loading...