Hassan Afzali-Kusha
Orcid: 0000-0002-3006-633X
According to our database1,
Hassan Afzali-Kusha
authored at least 13 papers
between 2015 and 2023.
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Bibliography
2023
X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory Units.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
2022
X-NVDLA: Runtime Accuracy Configurable NVDLA based on Employing Voltage Overscaling Approach.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the Approximate Computing, 2022
2020
Design Exploration of Energy-Efficient Accuracy-Configurable Dadda Multipliers With Improved Lifetime Based on Voltage Overscaling.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Low-power Accuracy-configurable Carry Look-ahead Adder Based on Voltage Overscaling Technique.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
2018
Energy and Reliability Improvement of Voltage-Based, Clustered, Coarse-Grain Reconfigurable Architectures by Employing Quality-Aware Mapping.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Energy Consumption and Lifetime Improvement of Coarse-Grained Reconfigurable Architectures Targeting Low-Power Error-Tolerant Applications.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2016
Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits.
Microelectron. Reliab., 2015
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies.
Integr., 2015
High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistors.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015